AN 696: Using the JESD204B MegaCore Function in Arria V Devices

Download PDF
ID 683843
Date 5/11/2015
Public
Document Table of Contents
Document Table of Contents x
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices x
1.1. JESD204B MegaCore Function Reference Design 1.2. Hardware and Software Requirements 1.3. Hardware Setup 1.4. Using the Reference Design 1.5. Using the System Console Tool to Execute Commands 1.6. JESD204B MegaCore Function Link initialization Sequences 1.7. Editing and Recompiling the Reference Design 1.8. Document Revision History
1.1. JESD204B MegaCore Function Reference Design x
1.1.1. SYSREF Generator 1.1.2. In-System Sources and Probes (ISSP) 1.1.3. Qsys System 1.1.4. File Directory and Content 1.1.5. Reference Design Initialization Sequence
1.3. Hardware Setup x
1.3.1. FPGA Pin Assignments 1.3.2. Status LED
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices

1.1.3. Qsys System

The reference design uses a simple Qsys system that consists of two components: the JTAG to Avalon Master Bridge and the Avalon-Memory Mapped (Avalon-MM) Slave Translator.

Follow the steps below to examine the Qsys system:

  1. Launch the Quartus II software.
  2. On the File menu, click Open.
  3. Browse and select the jesd204b_avmm_interface.qsys file located in the project directory.
  4. Click Open.

The Qsys system consists of the following components:

  • JTAG to Avalon Master Bridge—acts as the Avalon-MM master in the reference design, This component is the main communication channel between the System Console tool and the Avalon-MM slave translator in the design. The System Console tool accesses the RX registers of the JESD204B MegaCore function.
  • Avalon-MM Slave Translator—exports all required Avalon signals to the top-level design. With the Avalon signals exported, the Qsys system can interface with any Avalon-compliant component that resides outside of the Qsys component library.
Figure 3. Component Map of the Qsys SystemFor this reference design, the JESD204B MegaCore function is an Avalon-compliant component. Therefore, the Avalon-MM Slave Translator component must connect to the JTAG to Avalon Master Bridge component.


Table 4.  Memory Map of the Qsys System Memory map of the Qsys system for the Avalon-MM Slave Translator in this reference design.

Name

Component Name

Base Address

Description

merlin_slave_translator_0

Avalon-MM Slave Translator

0x000

Exports Avalon-MM signals to interface with the JESD204B MegaCore function.

Level Two Title