AN 696: Using the JESD204B MegaCore Function in Arria V Devices

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ID 683843
Date 5/11/2015
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Document Table of Contents
Document Table of Contents x
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices x
1.1. JESD204B MegaCore Function Reference Design 1.2. Hardware and Software Requirements 1.3. Hardware Setup 1.4. Using the Reference Design 1.5. Using the System Console Tool to Execute Commands 1.6. JESD204B MegaCore Function Link initialization Sequences 1.7. Editing and Recompiling the Reference Design 1.8. Document Revision History
1.1. JESD204B MegaCore Function Reference Design x
1.1.1. SYSREF Generator 1.1.2. In-System Sources and Probes (ISSP) 1.1.3. Qsys System 1.1.4. File Directory and Content 1.1.5. Reference Design Initialization Sequence
1.3. Hardware Setup x
1.3.1. FPGA Pin Assignments 1.3.2. Status LED
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices

1.3. Hardware Setup

You need to set up the development board before running the reference design.
Hardware Setup
  • The AD9250 module derives power from the FMC connector on the development board.
  • The AD9250 module supplies the device clock to FPGA 2.
  • For subclass 1 mode, the FPGA generates SYSREF for the JESD204B MegaCore function as well as the AD9250 module.


To set up the board connections, perform the following steps:

  1. Install the ADI AD9250 daughter card module to the FMC port (J9) on the development board as shown in figure.
  2. Connect the mini-USB cable to the mini USB connector (J7) on development board.
  3. Connect the power adapter shipped with the development board to the power supply jack (J6).
  4. Turn on the power.
    You are now ready to download the .sof file and program the FPGA device on the development board.

Section Content
FPGA Pin Assignments
Status LED

Level Two Title