AN 696: Using the JESD204B MegaCore Function in Arria V Devices

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ID 683843
Date 5/11/2015
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Document Table of Contents
Document Table of Contents x
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices x
1.1. JESD204B MegaCore Function Reference Design 1.2. Hardware and Software Requirements 1.3. Hardware Setup 1.4. Using the Reference Design 1.5. Using the System Console Tool to Execute Commands 1.6. JESD204B MegaCore Function Link initialization Sequences 1.7. Editing and Recompiling the Reference Design 1.8. Document Revision History
1.1. JESD204B MegaCore Function Reference Design x
1.1.1. SYSREF Generator 1.1.2. In-System Sources and Probes (ISSP) 1.1.3. Qsys System 1.1.4. File Directory and Content 1.1.5. Reference Design Initialization Sequence
1.3. Hardware Setup x
1.3.1. FPGA Pin Assignments 1.3.2. Status LED
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices

1.7. Editing and Recompiling the Reference Design

This section describes some editable parameters when interoperating with the AD9250 module. When you make modification to the JESD204B MegaCore function in the Quartus II software, you must make corresponding changes to the AD9250 configuration file.

The example below demonstrates the following parameter modification:

  • Subclass 1 to 0
  • K from 32 to 16
  • Disable the scrambler

To edit the JESD204B MegaCore function parameters and recompile the reference design, perform the following steps:

  1. On the Tools menu, click MegaWizard Plug-In Manager.
  2. Select Edit an existing custom megafunction variation, then click Next.
  3. Select the existing megafunction variation file (.v/.vhd/.vhdl) for the altera_jesd204 component, then click Next
  4. Edit the MegaCore parameters, then click Finish to close the parameter editor and generate the MegaCore.
  5. Open the jesd204b_ed_top.v file and change the localparam K value from 32 to 16.
  6. Use the text editor to change the following bit settings in the AD9250 module configuration file located in the /control_unit/ad9250_222.mif directory: 
    
•	At content line 22, 
change register 0x6E bit[7] from 1 to 0 to disable scrambling:  
10000001000000000110111000000001;

•	At content line 23, 
change register 0x70 bit[4] from 1 to 0 to set K = 16 (0x0F + 1):
10000001000000000111000000001111;

•	At content line 25, 
change register 0x73 bit[5] from 1 to 0 for subclass 0:
10000001000000000111001100001111;

•	At content line 26, 
change register 0x3A bit [2:0] from “111” to “000” to turn off 
SYSREF detection:
10000001000000000011101000000000;
  7. Optionally, if you want to rename the MIF, change the pointer to the MIF located in control_unit/control_unit.v. 
    
rom_1port #(
   .INIT_FILE ("./control_unit/<renamed MIF file>.mif"),
) u_rom0 (                       
   .clock   (clk),                    
   .clken   (rom_clken),
   .address (rom_addr_ptr),
   .q       (rom0_data_out)
);
  8. On the Processing menu, click Start Compilation.
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