AN 696: Using the JESD204B MegaCore Function in Arria V Devices

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ID 683843
Date 5/11/2015
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Document Table of Contents
Document Table of Contents x
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices x
1.1. JESD204B MegaCore Function Reference Design 1.2. Hardware and Software Requirements 1.3. Hardware Setup 1.4. Using the Reference Design 1.5. Using the System Console Tool to Execute Commands 1.6. JESD204B MegaCore Function Link initialization Sequences 1.7. Editing and Recompiling the Reference Design 1.8. Document Revision History
1.1. JESD204B MegaCore Function Reference Design x
1.1.1. SYSREF Generator 1.1.2. In-System Sources and Probes (ISSP) 1.1.3. Qsys System 1.1.4. File Directory and Content 1.1.5. Reference Design Initialization Sequence
1.3. Hardware Setup x
1.3.1. FPGA Pin Assignments 1.3.2. Status LED
1. AN 696: Using the JESD204B MegaCore Function in Arria V Devices

1.6. JESD204B MegaCore Function Link initialization Sequences

Upon device power up, assert reset using Tcl command in the System Console tool to trigger an initialization for the JESD204B MegaCore function link in the reference design.

The following list describes the link initialization sequence.

Table 9.  Link initialization Sequences and Observation
Sequence Description Activity Observation
1 The input of the link layer or the output of the PCS (jesd204_rx_pcs_data[63:0]) receives 0xBC or K28.5 (/K/) characters. Check both the lane1_cs_state and lane0_cs_state register identifiers by executing read_rxstatus4 command in the System Console tool to read the JESD204 RX status register. 0x02 is asserted at both lane1_cs_state[3:2] for lane 1 and lane0_cs_state[1:0] for lane 0, which indicates that code group synchronization (CGS) phase is detected. The receiver deasserts the synchronization request signal upon receiving four consecutive K28.5 characters. Then, the rx_dev_sync_n signal will be deasserted.
2 When 0x1C or K28.0 (/R/) character is received, the ILAS phase is detected. Check both the lane1_cs_state and lane0_cs_state register identifiers by executing read_rxstatus5 command in the System Console tool to read the JESD204 RX status register. 0x02 is asserted at both lane1_cs_state[3:2] for lane 1 and lane0_cs_state[1:0] for lane 0. The ILAS consists of four multiframes. The 1st, 3rd, and 4th multiframes begin with /R/ character and end with 0x7C or K28.3 (/A/) character. On the 2nd multiframe, the ADC transmits the JESD204B link configuration information to the receiver. The 2nd multiframe begins with /R/ character, followed by 0x9C or K28.4 (/Q/) character and ends with /A/ character.
3 User data phase enters after four multiframes of ILAS. Check both the lane1_dll_user_data_phase and lane0_dll_user_data_phase register identifiers by executing read_rxstatus7 command in the System Console tool to read the JESD204 RX status register. Both lane1_dll_user_data_phase1 of lane 1 & lane0_dll_user_data_phase0 of lane 0 are asserted. In this phase, the ADC transmits PRBS data to the FPGA.
4 All lanes are aligned, indicated by the assertion of the dev_lane_aligned signal. The link layer begins transmitting data to the transport layer. LED D29 illuminates to indicate that lane alignment is achieved.
5 Link initialization successful. Monitor the data integrity through the PRBS checker. The PRBS checker receives data from the transport layer and checks the received data against the internally generated PRBS polynomial data. The polynomial length and feedback tap position must be the same for both the ADC PRBS generator and the FPGA PRBS checker. The AD9250 module is set to output PRBS-9 data, with feedback tap of 5.
  • LED D33 is off to indicate no data error.
  • LED D31 and D32 are off to indicate that no interrupt signal is asserted because there is no error condition or a synchronization request.
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