1.1. JESD204B MegaCore Function Reference Design
The reference design contains a pregenerated JESD204B design example and peripherals like the SYSREF generator.
Figure 1. System Diagram
The system-level diagram shows how the different modules connect in this reference design.
In this setup where LMF = 222, the data rate of the both transceiver lanes is 4.915 Gbps. The AD9517 clock generator provides 122.88 MHz clock to the FPGA and 245.76 MHz sampling clock to both AD9250 devices. The transceiver CDR PLL input reference clock (pll_ref_clk) uses the FPGA clock to generate the frame clock and link clock.
The reference design consists of the following modules:
- JESD204B MegaCore function design example
- Duplex JESD204B MegaCore function
- TX & RX transport layer
- core PLL
- transceiver reconfiguration controller
- transceiver reset controllers
- control unit
- SPI master
- SYSREF generator
- In-System Sources and Probes (ISSP)
- Qsys System
The design example also contains a parallel pseudorandom-binary-sequence (PRBS) data generator and checker. The data generator generates a PRBS9 data pattern and the data checker verifies the PRBS9 data received. The checker flags an error when it finds a mismatch of data sample. You can monitor the data checker's error flag using the status LED on the development board or the Signal Tap II Logic Analyzer tool.
The reference design implements the JESD204B MegaCore function with the following parameter configuration.
| Parameter | Value | Description |
|---|---|---|
| Subclass | 1 | Subclass mode |
| L | 2 | Number of lanes per converter device |
| M | 2 | Number of converters per device |
| F | 2 | Number of octets per frame |
| S | 1 | Number of transmitted samples per converter per frame |
| N | 14 | Number of conversion bits per converter |
| N' | 16 | Number of transmitted bits per sample (JESD204 word size, which is in nibble group) |
| K | 32 | Number of frames per multiframe |
| CS | 0 | Number of control bits per conversion sample |
| CF | 0 | Number of control words per frame clock period per link |
| HD | 0 | High Density user data format |
| SCR | On | Enable scramble |
| FRAMECLK_DIV | 1 | The divider ratio of the frame_clk |
You need to configure both the AD9517 clock generator and AD9250 ADC module for normal operation. Between the FPGA and CPLD (on the AD9250 module), a 4-wire SPI configures the clock generator and ADC. The CPLD, which acts as an SPI slave, uses the first 8-bits of the 32-bits SPI transaction as the preselection bits to configure the clock generator, converter 1 (ADC #1), or converter 2 (ADC #2). The remaining 24-bits follow the SPI interface timing requirements as listed in the AD9517 and AD9250 datasheet.
| Module | Description | Preselection Byte |
|---|---|---|
| AD9250 | ADC #1 | 0x80 |
| AD9250 | ADC #2 | 0x81 |
| AD9517 | Clock generator | 0x84 |
The FPGA, which acts as an SPI master, writes the SPI instruction and register data following the sequence and content in ROM-1 port of the memory initialization file (MIF). Figure shows a timing diagram for the correlation between the bit settings in MIF and the write instruction.
Figure 2. Write Instruction to AD9517/AD9250 Registers Timing Diagram