AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

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ID 683778
Date 3/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design 2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design 3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design 4. Functionality Level and Resource Utilization Estimates 5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design 6. Document Revision History for the AN 896: Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design x
1.1. Features of the Reference Design 1.2. Structure of the Reference Design Archive
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design x
2.1. Reference Design Architecture 2.2. Reference Design Component Blocks 2.3. Design Components and Parameter Options 2.4. Output Voltage Data Formats and Related Parameters
2.3. Design Components and Parameter Options x
2.3.1. Reset Sequencer (Reset_Sequencer) 2.3.2. Modular ADC Core Intel® FPGA IP (ADC_Core) 2.3.3. Sequencer ADC Decoder (ADC_Decoder) 2.3.4. Sequencer Voltage Monitor (Sequencer_VMonitor) 2.3.5. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave) 2.3.6. Power Sequencer (Sequencer_Core) 2.3.7. Other Design Components
2.3.3. Sequencer ADC Decoder (ADC_Decoder) x
2.3.3.1. Sequencer ADC Decoder Parameter Settings
2.3.4. Sequencer Voltage Monitor (Sequencer_VMonitor) x
2.3.4.1. Sequencer Voltage Monitor Parameter Settings
2.3.6. Power Sequencer (Sequencer_Core) x
2.3.6.1. Power Sequencer Parameter Settings
2.3.7. Other Design Components x
2.3.7.1. POR Pulse (POR_Pulse) 2.3.7.2. Reset to Conduit Adapter (Reset2Conduit) 2.3.7.3. pll_lock_splitter (PLL_LockSplit) 2.3.7.4. Avalon®-MM Sequencer (AVMM_Initializer)
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design x
3.1. Customizing and Generating the Design Example 3.2. Updating the Schematic After Customizing the Design 3.3. Assigning Pins and Compiling the Design Example 3.4. Testbench Simulation to Understand Design Behavior
3.3. Assigning Pins and Compiling the Design Example x
3.3.1. Pin Description
3.4. Testbench Simulation to Understand Design Behavior x
3.4.1. Generating the Testbench Simulation 3.4.2. Running the Testbench Simulation
4. Functionality Level and Resource Utilization Estimates x
4.1. PMBus* Commands Implementation 4.2. Resource Utilization of the Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
4. Functionality Level and Resource Utilization Estimates
5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design
6. Document Revision History for the AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

2.3.6. Power Sequencer (Sequencer_Core)

The Power Sequencer component implements the decision-making state machine and delay timer for sequencing the output rails. This component is a standalone block that will provide the most minimal design implementation if you do not need voltage rail monitoring and PMBus* control.

The Power Sequencer component determines when to sequence the power regulators up or down based on the power good input levels. It provides the enable and discharge output signals to the power regulators.

Figure 11.  Power Sequencer Parameter Editor


If you want to enable or disable multiple rails simultaneously, you can combine the rails into a single group. The design conjoins (logically ANDs) the power good signals of groups with the same Power Group Number setting. These groups also share the same enable output and discharge output. Power rails within the same group must have the same values for the Sequencer Delay and Qualification Window parameters. Otherwise, the Platform Designer displays a warning message.

If you disable power groups, the Power Group Number column in the table is read-only and each VOUT rail has its own unique power group number.

For example, using the settings in the preceding figure, the sequencer behaves in the following manner:

  • The rails for VOUT0, VOUT2, and VOUT3 share the same enable signal and the rails ramp up together.
  • After the power good inputs for all those rails go high—occuring within the 10 ms qualification window—the enable signal for VOUT1 asserts following a 10 µs delay.
  • After the power good input for VOUT1 goes high—occuring within the 10 ms qualification window—the enable signals for VOUT4 and VOUT5 assert following a 10 µs delay.
  • After the power good inputs for both VOUT4 and VOUT5 go high—within the 10 ms qualification window—the sequencer completes ramping up all six rails in the three power groups.
Note: The delay between a power good input going high and the next enable being asserted does not depend only on the value of the Sequencer Delay parameter. The total delay also includes the additional delay caused by debouncing power good inputs and the delay caused by the number of ADC samples the Sequencer Voltage Monitor component checks.

While the Multi-Rail Power Sequencer and Monitor design is in a normal operational state and all of the rails are enabled, if a power good signal from one of the VOUT rails deasserts, the sequencer immediately asserts the nFAULT signal and gracefully enters a power down sequence.

If you enable retries in the Sequencer Voltage Monitor component, the Power Sequencer component performs the following steps:

  1. Waits for all power good signals to deassert
  2. Waits for the duration of the specified delay time between retries
  3. Attempts a power up sequence

When the Power Sequencer component attempts a power up sequence, the nFAULT signal automatically clears. If the failure persists and you do not set Retry Attempts parameter in Sequencer Voltage Monitor component to Infinite, the nFAULT signal continues to toggle until it reaches the maximum number of retries. If the failure still persists after that, the nFAULT signal remains asserted, unless you reset the sequencer in one of these ways:

  • Toggle the ENABLE signal
  • Use a PMBus* command to increase the number of retries

Section Content
Power Sequencer Parameter Settings

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