4.1. PMBus* Commands Implementation

AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

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ID 683778

Date 4/24/2025

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4.1. PMBus* Commands Implementation

The design implements different register control and status commands, depending on the functionality level you select in the Sequencer Monitor component. The commands can address one or two bytes of data. The design stores all data for the output voltage and related parameters in the DIRECT format.

Table 9. Power Sequencer PMBus* Commands DescriptionThis table lists the supported PMBus* commands. The design implements commands marked with * only if you select the Full-featured option for the Functionality Level parameter of the Sequencer Monitor component. Items with either a * or # are not implemented for digitally monitored rails. The Manufacturer-Specific commands (starting with command 0xC4) are only implemented when non-volatile error logging is enabled.
Command Code (Address)	Bit	Name		Scope	SMBus Transaction	Description
`0x00`	[7:0]	PAGE		Common	Read Byte Write Byte	Selects the page of commands for the voltage rail being accessed. Range of valid page values is `0x00` to `0x8F` (143) and relates to each `VOUT` rail.
`0x03`	—	CLEAR_FAULTS		Common	Send Byte	Clears all warnings and faults in the write-to-clear status bits across all pages.
`0x35`	[15:0]	VIN_ON ¹	*	Common	Read Word Write Word	Sets the value of the input voltage at which it is sufficiently high for the design to begin sequencing the output rails on.
`0x36`	[15:0]	VIN_OFF ¹	*	Common	Read Word Write Word	Sets the value of the input voltage at which it has dropped low enough that the design must sequence the output rails off.
`0x40`	[15:0]	VOUT_OV_FAULT_LIMIT ¹	*	Page	Read Word Write Word	Sets the value of the output voltage that causes an output overvoltage fault.
`0x41`	—	VOUT_OV_FAULT_RESP	#	—	Read Byte Write Byte	Instructs the device on the action to take when there is an output overvoltage fault for the rail selected by the current PAGE.
	[7:6]	Response	#	Page	—	00—Continue operation without interruption 01—Invalid 10—Sequence a power down in reverse order and respond according to the retry setting in bits [5:3] 11—Invalid
	[5:3]	Retry Setting ²	#	Common	—	Indicates the number of times the device attempts to restart from a fault. 0—Do not attempt a restart and remain disabled until the fault clears and `ENABLE` input toggles 1 to 6—Retry for the specified number of attempts, then stop and remain disabled until the fault clears and the `ENABLE` input toggles 7—Retry infinitely Note: The Retry Setting is a global setting for the sequencer.
	[2:0]	Delay Time ³	#	Common	—	Specifies the delay interval between attempts to restart. 0—No delay 1 to 7—Use the Delay Time Between Restarts parameter setting in the Power Sequencer component Note: The Delay Time is a global setting for the sequencer.
`0x42`	[15:0]	VOUT_OV_WARN_LIMIT ¹	*	Page	Read Word Write Word	Sets the value of the output voltage that causes an output overvoltage warning for the rail selected by the current PAGE.
`0x43`	[15:0]	VOUT_UV_WARN_LIMIT ¹	*	Page	Read Word Write Word	Sets the value of the output voltage that causes an output undervoltage warning for the rail selected by the current PAGE.
`0x44`	[15:0]	VOUT_UV_FAULT_LIMIT ¹	*	Page	Read Word Write Word	Sets the value of the output voltage that causes an output undervoltage fault for the rail selected by the current PAGE .
`0x45`	—	VOUT_UV_FAULT_RESP		—	Read Byte Write Byte	Instructs the device on the action to take when there is an output undervoltage fault for the rail selected by the current PAGE.
	[7:6]	Response		Page	—	00—Continue operation without interruption 01—Invalid 10—Sequence a power down in reverse order and respond according to the retry setting in bits [5:3] 11—Invalid
	[5:3]	Retry Setting²		Common	—	Indicates the number of times the device attempts to restart from a fault. 0—Do not attempt a restart and remain disabled until the fault clears and `ENABLE` input toggles 1 to 6—Retry for the specified number of attempts, then stop and remain disabled until the fault clears and the `ENABLE` input toggles 7—Retry infinitely Note: The Retry Setting is a global setting for the sequencer.
	[2:0]	Delay Time³		Common	—	Specifies the delay interval between attempts to restart. 0—No delay 1 to 7—Use the Delay Time Between Restarts parameter setting in the Power Sequencer component Note: The Delay Time is a global setting for the sequencer.
`0x55`	[15:0]	VIN_OV_FAULT_LIMIT ¹	*	Common	Read Word Write Word	Sets the value of the input voltage that causes an input overvoltage fault.
`0x56`	—	VIN_OV_FAULT_RESP	#	—	Read Byte Write Byte	Instructs the device on the action to take when there is an input overvoltage fault.
	[7:6]	Response	#	Common	—	00—Continue operation without interruption 01—Invalid 10—Sequence a power down in reverse order and respond according to the retry setting in bits [5:3] 11—Invalid
	[5:3]	Retry Setting²	#	Common	—	Indicates the number of times the device attempts to restart from a fault. 0—Do not attempt a restart and remain disabled until the fault clears and `ENABLE` input toggles 1 to 6—Retry for the specified number of attempts, then stop and remain disabled until the fault clears and the `ENABLE` input toggles 7—Retry infinitely Note: The Retry Setting is a global setting for the sequencer.
	[2:0]	Delay Time³	#	Common	—	Specifies the delay interval between attempts to restart. 0—No delay 1 to 7—Use the Delay Time Between Restarts parameter setting in the Power Sequencer component Note: The Delay Time is a global setting for the sequencer.
`0x57`	[15:0]	VIN_OV_WARN_LIMIT ¹	*	Common	Read Word Write Word	Sets the value of the input voltage that causes an input overvoltage warning.
`0x58`	[15:0]	VIN_UV_WARN_LIMIT ¹	*	Common	Read Word Write Word	Sets the value of the input voltage that causes an input undervoltage warning.
`0x59`	[15:0]	VIN_UV_FAULT_LIMIT ¹	*	Common	Read Word Write Word	Sets the value of the input voltage that causes an input undervoltage fault.
`0x5A`	—	VIN_UV_FAULT_RESP		—	Read Byte Write Byte	Instructs the device on the action to take when there is an input undervoltage fault.
	[7:6]	Response		Common	—	00—Continue operation without interruption 01—Invalid 10—Sequence a power down in reverse order and respond according to the retry setting in bits [5:3] 11—Invalid
	[5:3]	Retry Setting²		Common	—	Indicates the number of times the device attempts to restart from a fault. 0—Do not attempt a restart and remain disabled until the fault clears and `ENABLE` input toggles 1 to 6—Retry for the specified number of attempts, then stop and remain disabled until the fault clears and the `ENABLE` input toggles 7—Retry infinitely Note: The Retry Setting is a global setting for the sequencer.
	[2:0]	Delay Time³		Common	—	Specifies the delay interval between attempts to restart. 0—No delay 1 to 7—Use the Delay Time Between Restarts parameter setting in the Power Sequencer component Note: The Delay Time is a global setting for the sequencer.
`0x5E`	[15:0]	POWER_GOOD_ON ¹	*	Common	Read Word Write Word	Sets the value of the output voltage at which it is sufficiently high for the design to assert the `POWER_GOOD` signal to the Power Sequencer component, indicating that the output voltage is valid.
`0x5F`	[15:0]	POWER_GOOD_OFF ¹	*	Common	Read Word Write Word	Sets the value of the output voltage at which it has dropped low enough for the design to deassert the `POWER_GOOD` signal to the Power Sequencer component, indicating that the output voltage is not valid.
`0x78`	[7:0]	STATUS_BYTE [7]: BUSY [6]: OFF [5]: VOUT_OV_FAULT [4]: Reserved [3]: VIN_UV_FAULT [2]: Reserved [1]: CML [0]: NONE_OF_THE_ABOVE		Page	Read Byte	A value of `1` for any bit indicates that a fault or warning has occurred in the associated status registers.
`0x79`	[15:0]	STATUS_WORD [15]: VOUT [14]: Reserved [13]: INPUT [12]: MFRSPECIFIC [11]: PG_STATUS# [10]: Reserved [9]: OTHER [8]: UNKNOWN [7]: BUSY [6]: OFF [5]: VOUT_OV_FAULT [4]: Reserved [3]: VIN_UV_FAULT [2]: Reserved [1]: CML [0]: NONE_OF_THE_ABOVE		Page	Read Word	A value of `1` for any bit indicates that a fault or warning has occurred in the associated status registers. Bits [7:0] are duplicate of STATUS_BYTE.
`0x7A`	[7:0]	STATUS_VOUT [7]: VOUT_OV_FAULT [6]: VOUT_OV_Warning [5]: VOUT_UV_Warning [4]: VOUT_UV_FAULT [3]: Reserved [2]: Reserved [1]: Reserved [0]: Reserved		Page	Read Byte Write Byte	A value of `1` for any bit indicates that a fault or warning has occurred and flagged for the various conditions. To clear the flag, write `1` to the particular bit in the register.
`0x7C`	[7:0]	STATUS_INPUT [7]: VIN_OV_FAULT [6]: VIN_OV_Warning [5]: VIN_UV_Warning [4]: VIN_UV_FAULT [3]: Unit Off for Low VIN [2]: Reserved [1]: Reserved [0]: Reserved		Common	Read Byte Write Byte	A value of `1` for any bit indicates that a fault or warning has occurred and flagged for the various conditions. To clear the flag, write `1` to the particular bit in the register.
`0x7E`	[7:0]	STATUS_CML [7]: Invalid/Unsupported Command [6]: Invalid/Unsupported Data [5]: Reserved [4]: Reserved [3]: Reserved [2]: Reserved [1]: Reserved [0]: Reserved		Page	Read Byte Write Byte	A value of `1` for any bit indicates that a fault or warning has occurred and flagged for the various conditions. To clear the flag, write `1` to the particular bit in the register.
`0x7F`	[7:0]	STATUS_OTHER [7]: Reserved [6]: Reserved [5]: Reserved [4]: Reserved [3]: Reserved [2]: Reserved [1]: Reserved [0]: First to Assert SMBALERT#		Page	Read Byte Write Byte	A value of `1` for any bit indicates that a fault or warning has occurred and flagged for the various conditions. To clear the flag, write `1` to the particular bit in the register.
`0x88`	[15:0]	READ_VIN ¹	#	Common	Read Word	Indicates the present input voltage level.
`0x8B`	[15:0]	READ_VOUT ¹	#	Page	Read Word	Indicates the present output voltage level for the rail selected by the current PAGE.
`0xC4`	[31:0]	MFR_TOD		Common	Read 32 Write 32	Time of Day Counter: Returns seconds counted since 1/1/2020 when read; initializes to '0', settable on write.
`0xC5`	[31:0]	MFR_TOD_ADJUST		Common	Read 32 Write 32	Time of Day Adjustment: Number of system clock ticks in 1 second. Can be adjusted to tune for variances in reference clock frequency. Default—reference clock frequency
`0xD0`	[31:0]	MFR_NV_CONTROL [31:24]: Total Log Entries (RO) [23:16]: Current read index [15:8]: Reserved [7:4]: Black Box page offset [3:1]: Reserved [0]: Clear Log (1S)		Common	Read 32 Write 32	NV Flash Log: Master & Non-Paged Enable Register 31 to 24—Indicates the total number of logged entries. 23 to 16—Sets the current fault index for reading the log from flash 7 to 4—These bits are used when reading the Black Box data. It is an offset to specify which pages are read. 0—Clears the entire log. It is a write-to-clear bit.
`0xD1`	[7:0]	MFR_NV_MASTER_EN [7:4]: Reserved [3]: VIN_UV Fault Log Ena [2]: VIN_OV Fault Log Ena [1]: Black Box Enable [0]: Global Log Enable		Common	Read Byte Write Byte	NV Flash Log: Master & Non-Paged Enable Register 3—Enables logging of VIN_UV Faults. 2—Enables logging of VIN_OV Faults. 1—A global enable to allow logging the Black Box data. 0—A global enable to allow logging of any fault or Black Box data.
`0xD2`	[7:0]	MFR_NV_PAGE_EN [7:3]: Reserved [2]: Qual Window Log Ena [1]: VOUT_UV Fault Log Ena [0]: VOUT_OV Fault Log Ena		Common	Read Byte Write Byte	NV Flash Log: Page Enable Register This set of registers is dependent on the value in PAGE to affect the associated enable signals. 2—Enables logging a qualification window timeout error when sequencing "on" for a given voltage rail, if it does not report the power to be good within the required time window. 1—Enables logging of VOUT_UV Faults. 0—Enables logging of VOUT_OV Faults.
`0xD4`	[15:0]	MFR_NV_ERRLOG_DAT [15:8]: Fault type [7:0]: Page number		Common	Read Word	NV Flash Log: Error Log Reads data stored in the error log, specified by the read index in MFR_NV_CTRL[23:16]. Fault type value: [12]—Qualification Window Timeout [11]—VIN_UV Fault [10]—VIN_OV Fault [9]—VOUT_UV Fault [8]—VOUT_OV Fault
`0xD5`	[31:0]	MFR_NV_ERRLOG_BBDAT [31:30]: Rail status, rail n +15 [29:28]: Rail status, rail n +14 [27:26]: Rail status, rail n +13 [25:24]: Rail status, rail n +12 [23:22]: Rail status, rail n +11 [21:20]: Rail status, rail n +10 [19:18]: Rail status, rail n +9 [17:16]: Rail status, rail n +8 [15:14]: Rail status, rail n +7 [13:12]: Rail status, rail n +6 [11:10]: Rail status, rail n +5 [9:8]: Rail status, rail n +4 [7:6]: Rail status, rail n +3 [5:4]: Rail status, rail n +2 [3:2]: Rail status, rail n +1 [1:0]: Rail status, rail n		Common	Read 32	NV Flash Log: Black Box Data The Black Box data stores log entries of the current status for each rail. The read index and page offset is specified by MFR_NV_CONTROL its [23:16] and [7:4] For MFR_NV_CONTROL[7:4] = 0x0, it provides the status for VOUT rails 14:0 and VIN. For MFR_NV_CONTROL[7:4] = 0x1, it would provide the status for rails 30:15, and so on. Rail status: 11—Rail ON/stable 10—OV detected 01—UV detected 00—Rail OFF
`0xD6`	[31:0]	MFR_NV_ERRLOG_TOD		Common	Read 32	NV Flash Log: Error Timestamp Timestamp for error logged. Returns seconds counted since 1/1/2020.

¹ The levels are specified in the PMBus* DIRECT format. For information about translating to and from the DIRECT format, refer to the related information.

² The Retry Setting value is common across all pages, and warnings or faults. The controller attempts to recover after a fault until it reaches the global number of times to retry. The retry counter resets whenever the ENABLE input toggles low. The Response setting for this same command is unique to each warning or fault.

³ The Delay Time setting is common across all pages, and warnings or faults. After all power good signals deasserts, the controller waits between retry attempts for the specified time before power sequencing the rails back up. The Response setting for this same command is unique to each warning or fault.

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AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

4.1. PMBus* Commands Implementation