AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

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ID 683778
Date 3/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design 2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design 3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design 4. Functionality Level and Resource Utilization Estimates 5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design 6. Document Revision History for the AN 896: Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design x
1.1. Features of the Reference Design 1.2. Structure of the Reference Design Archive
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design x
2.1. Reference Design Architecture 2.2. Reference Design Component Blocks 2.3. Design Components and Parameter Options 2.4. Output Voltage Data Formats and Related Parameters
2.3. Design Components and Parameter Options x
2.3.1. Reset Sequencer (Reset_Sequencer) 2.3.2. Modular ADC Core Intel® FPGA IP (ADC_Core) 2.3.3. Sequencer ADC Decoder (ADC_Decoder) 2.3.4. Sequencer Voltage Monitor (Sequencer_VMonitor) 2.3.5. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave) 2.3.6. Power Sequencer (Sequencer_Core) 2.3.7. Other Design Components
2.3.3. Sequencer ADC Decoder (ADC_Decoder) x
2.3.3.1. Sequencer ADC Decoder Parameter Settings
2.3.4. Sequencer Voltage Monitor (Sequencer_VMonitor) x
2.3.4.1. Sequencer Voltage Monitor Parameter Settings
2.3.6. Power Sequencer (Sequencer_Core) x
2.3.6.1. Power Sequencer Parameter Settings
2.3.7. Other Design Components x
2.3.7.1. POR Pulse (POR_Pulse) 2.3.7.2. Reset to Conduit Adapter (Reset2Conduit) 2.3.7.3. pll_lock_splitter (PLL_LockSplit) 2.3.7.4. Avalon®-MM Sequencer (AVMM_Initializer)
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design x
3.1. Customizing and Generating the Design Example 3.2. Updating the Schematic After Customizing the Design 3.3. Assigning Pins and Compiling the Design Example 3.4. Testbench Simulation to Understand Design Behavior
3.3. Assigning Pins and Compiling the Design Example x
3.3.1. Pin Description
3.4. Testbench Simulation to Understand Design Behavior x
3.4.1. Generating the Testbench Simulation 3.4.2. Running the Testbench Simulation
4. Functionality Level and Resource Utilization Estimates x
4.1. PMBus* Commands Implementation 4.2. Resource Utilization of the Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
4. Functionality Level and Resource Utilization Estimates
5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design
6. Document Revision History for the AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

2.3.3. Sequencer ADC Decoder (ADC_Decoder)

The Sequencer ADC Decoder component decodes up to 16 Avalon® Streaming ( Avalon® -ST) ADC interfaces to sets of voltage level busses. Depending on which device you choose, each Avalon® -ST ADC interface can contain voltage levels of up to nine or 17 analog input channels. The sequencer allows a total of 144 monitored voltage levels.

Additionally, the Sequencer ADC Decoder component allows you to map any of the voltage level busses or external POK signals to any monitored VOUT or VIN rail. The configurable options allow you to specify the number of VOUT rails, the number of ADC interfaces, the number of power good inputs (POK signals), and how long to debounce the power good inputs.

The debouncer passes through the POK signal only after it has been stable for the duration of the debounce interval. You can select from 28 levels of debounce. The duration of the interval depends on the clock frequency that you provide to the component.

Figure 8.  Sequencer ADC Decoder Parameter Editor


The progression of the debounce level is exponential in time. The parameter editor of the Sequencer ADC Decoder component calculates the debounce duration only after the clock of the component connects to the system clock in Platform Designer. Otherwise, the parameter editor does not make any calculation and the Component’s Clock Frequency box displays 0 MHz.

For every VIN and VOUT rail, you can select the source for the ADC Interface/PG input and the ADC/PG Channel. Typically, select a unique interface and channel combination for each rail. If you set multiple rails to the same combination, the parameter editor displays a warning message. However, the Quartus® Prime software still allows you to generate the system if that is what you want.


Section Content
Sequencer ADC Decoder Parameter Settings

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