AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

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ID 683778
Date 3/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design 2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design 3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design 4. Functionality Level and Resource Utilization Estimates 5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design 6. Document Revision History for the AN 896: Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design x
1.1. Features of the Reference Design 1.2. Structure of the Reference Design Archive
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design x
2.1. Reference Design Architecture 2.2. Reference Design Component Blocks 2.3. Design Components and Parameter Options 2.4. Output Voltage Data Formats and Related Parameters
2.3. Design Components and Parameter Options x
2.3.1. Reset Sequencer (Reset_Sequencer) 2.3.2. Modular ADC Core Intel® FPGA IP (ADC_Core) 2.3.3. Sequencer ADC Decoder (ADC_Decoder) 2.3.4. Sequencer Voltage Monitor (Sequencer_VMonitor) 2.3.5. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave) 2.3.6. Power Sequencer (Sequencer_Core) 2.3.7. Other Design Components
2.3.3. Sequencer ADC Decoder (ADC_Decoder) x
2.3.3.1. Sequencer ADC Decoder Parameter Settings
2.3.4. Sequencer Voltage Monitor (Sequencer_VMonitor) x
2.3.4.1. Sequencer Voltage Monitor Parameter Settings
2.3.6. Power Sequencer (Sequencer_Core) x
2.3.6.1. Power Sequencer Parameter Settings
2.3.7. Other Design Components x
2.3.7.1. POR Pulse (POR_Pulse) 2.3.7.2. Reset to Conduit Adapter (Reset2Conduit) 2.3.7.3. pll_lock_splitter (PLL_LockSplit) 2.3.7.4. Avalon®-MM Sequencer (AVMM_Initializer)
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design x
3.1. Customizing and Generating the Design Example 3.2. Updating the Schematic After Customizing the Design 3.3. Assigning Pins and Compiling the Design Example 3.4. Testbench Simulation to Understand Design Behavior
3.3. Assigning Pins and Compiling the Design Example x
3.3.1. Pin Description
3.4. Testbench Simulation to Understand Design Behavior x
3.4.1. Generating the Testbench Simulation 3.4.2. Running the Testbench Simulation
4. Functionality Level and Resource Utilization Estimates x
4.1. PMBus* Commands Implementation 4.2. Resource Utilization of the Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
4. Functionality Level and Resource Utilization Estimates
5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design
6. Document Revision History for the AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

3.2. Updating the Schematic After Customizing the Design

After sequencer code generation, if you make changes that affect the top level design, you must update the top-level schematic accordingly to match the customizations.

For example:

  • If you remove the PMBus* Slave to Avalon®-MM Master Bridge component, you must remove the SMB_SCL and SMB_SDA signals too.
  • If you increase or decrease the number of rails, you must change the widths of the VRAIL_POK, VRAIL_ENA, and VRAIL_DCHG signals accordingly.
Figure 15. Updating Symbol in Top-Level Schematic of the Sequencer Component


  1. In the Project Navigator, double click the sequencer block diagram file to open it in the Block Editor window.
  2. In the sequencer schematic, right-click on the sequencer_qsys block and select Update Symbol or Block.
    The sequencer_qsys block updates. For example, the update removes the PMBus* ports and decreases the bus widths of the vrail_ena and vrail_dchg ports from six bits to four bits.
  3. Edit the connections from the I/O signals to the sequencer_qsys block.
    For example, remove the SMB_SCL and SMB_SDA signals that are not used anymore. Then, edit the bus widths of the VRAIL_ENA and VRAIL_DCHG signals and reconnect them back to the vrail_ena and vrail_dchg ports.
    Figure 16. Correcting the I/O Connections in the Top Level Schematic
  4. Save the sequencer schematic and close the Block Editor window.
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