Intel® MAX® 10 General Purpose I/O User Guide

Download PDF
ID 683751
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 I/O Overview 2. Intel® MAX® 10 I/O Architecture and Features 3. Intel® MAX® 10 I/O Design Considerations 4. Intel® MAX® 10 I/O Implementation Guides 5. GPIO Lite Intel® FPGA IP References 6. Intel® MAX® 10 General Purpose I/O User Guide Archives 7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide
1. Intel® MAX® 10 I/O Overview x
1.1. Intel® MAX® 10 Devices I/O Resources Per Package 1.2. Intel® MAX® 10 I/O Vertical Migration Support
2. Intel® MAX® 10 I/O Architecture and Features x
2.1. Intel® MAX® 10 I/O Standards Support 2.2. Intel® MAX® 10 I/O Elements 2.3. Intel® MAX® 10 I/O Buffers 2.4. I/O Standards Termination
2.1. Intel® MAX® 10 I/O Standards Support x
2.1.1. Intel® MAX® 10 I/O Standards Voltage and Pin Support
2.2. Intel® MAX® 10 I/O Elements x
2.2.1. Intel® MAX® 10 I/O Banks Architecture 2.2.2. Intel® MAX® 10 I/O Banks Performance 2.2.3. Intel® MAX® 10 I/O Banks Locations
2.3. Intel® MAX® 10 I/O Buffers x
2.3.1. Schmitt-Trigger Input Buffer 2.3.2. Programmable I/O Buffer Features
2.3.2. Programmable I/O Buffer Features x
2.3.2.1. Programmable Open Drain 2.3.2.2. Programmable Bus Hold 2.3.2.3. Programmable Pull-Up Resistor 2.3.2.4. Programmable Current Strength 2.3.2.5. Programmable Output Slew Rate Control 2.3.2.6. Programmable IOE Delay 2.3.2.7. PCI Clamp Diode 2.3.2.8. Programmable Pre-Emphasis 2.3.2.9. Programmable Differential Output Voltage 2.3.2.10. Programmable Emulated Differential Output 2.3.2.11. Programmable Dynamic Power Down
2.4. I/O Standards Termination x
2.4.1. Voltage-Referenced I/O Standards Termination 2.4.2. Differential I/O Standards Termination 2.4.3. Intel® MAX® 10 On-Chip I/O Termination
2.4.3. Intel® MAX® 10 On-Chip I/O Termination x
2.4.3.1. OCT Calibration 2.4.3.2. RS OCT in Intel® MAX® 10 Devices
3. Intel® MAX® 10 I/O Design Considerations x
3.1. Guidelines: VCCIO Range Considerations 3.2. Guidelines: Voltage-Referenced I/O Standards Restriction 3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules 3.5. Guidelines: I/O Restriction Rules 3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin 3.7. Guidelines: Analog-to-Digital Converter I/O Restriction 3.8. Guidelines: External Memory Interface I/O Restrictions 3.9. Guidelines: Dual-Purpose Configuration Pin 3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin x
3.6.1. Calculating the Total Inductance for 1.0 V Pin Placement
4. Intel® MAX® 10 I/O Implementation Guides x
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP 4.2. Verifying Pin Migration Compatibility
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP x
4.1.1. GPIO Lite Intel® FPGA IP Data Paths
4.1.1. GPIO Lite Intel® FPGA IP Data Paths x
4.1.1.1. DDR Input Path 4.1.1.2. DDR Output Path with Output Enable
5. GPIO Lite Intel® FPGA IP References x
5.1. GPIO Lite Intel® FPGA IP Parameter Settings 5.2. GPIO Lite Intel® FPGA IP Interface Signals
1. Intel® MAX® 10 I/O Overview
2. Intel® MAX® 10 I/O Architecture and Features
3. Intel® MAX® 10 I/O Design Considerations
4. Intel® MAX® 10 I/O Implementation Guides
5. GPIO Lite Intel® FPGA IP References
6. Intel® MAX® 10 General Purpose I/O User Guide Archives
7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide

3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package

There is strong inductive coupling on the Intel® MAX® 10 E144 lead frame package. Glitch may occur on an input pin when an aggressor pin with strong drive strength toggles directly adjacent to it.

PLL Clock Input Pins

The PLL clock input pins are sensitive to SSN jitter. To avoid the PLL from losing lock, do not use the output pins directly on the left and right of the PLL clock input pins.

Data Input Pins

Potential glitch on the data input pin, leading to input read signal failure, can occur in the following conditions:
  • The output pin directly adjacent to the data input pin is assigned an unterminated I/O standard, such as LVTTL and LVCMOS, with drive strength of 8 mA or higher.
  • The output pin directly adjacent to the data input pin is assigned a terminated I/O standard, such as SSTL, with drive strength of 8 mA or higher.

Intel recommends that you implement these guidelines to reduce jitter on the data input pin:

  • For unterminated I/O standards, implement one of these guidelines:
    • For the directly-adjacent output pin with these unterminated I/O standards, reduce the drive strength as follows:
      • 2.5 V, 3.0 V, and 3.3 V—reduce to 4 mA or below
      • 1.2 V, 1.5 V, and 1.8 V—reduce to 6 mA or below
    • Assign the pins directly on the left and right of the data input pin to a non-toggling signal.
    • Change the data input pin to a Schmitt Trigger input buffer for better noise immunity. If you are using Schmitt Trigger input buffer on the data input pin, you can use the directly-adjacent output pin with unterminated I/O standard at a maximum drive strength of 8 mA.
  • For terminated I/O standard, you can use only one pin directly on the left or right of the data input pin as toggling signal, provided that you set the slew rate setting of this pin to “0” (slow slew rate). Otherwise, assign the pins directly on the left and right of the data input pin to a non-toggling signal.
Level Two Title