MAX® 10 General Purpose I/O User Guide

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ID 683751
Date 3/17/2025
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 I/O Overview 2. MAX® 10 I/O Architecture and Features 3. MAX® 10 I/O Design Considerations 4. MAX® 10 I/O Implementation Guides 5. GPIO Lite Intel® FPGA IP References 6. MAX® 10 General Purpose I/O User Guide Archives 7. Document Revision History for the MAX® 10 General Purpose I/O User Guide
1. MAX® 10 I/O Overview x
1.1. MAX® 10 Devices I/O Resources Per Package 1.2. MAX® 10 I/O Vertical Migration Support
2. MAX® 10 I/O Architecture and Features x
2.1. MAX® 10 I/O Standards Support 2.2. MAX® 10 I/O Elements 2.3. MAX® 10 I/O Buffers 2.4. I/O Standards Termination
2.1. MAX® 10 I/O Standards Support x
2.1.1. MAX® 10 I/O Standards Voltage and Pin Support
2.2. MAX® 10 I/O Elements x
2.2.1. MAX® 10 I/O Banks Architecture 2.2.2. MAX® 10 I/O Banks Performance 2.2.3. MAX® 10 I/O Banks Locations
2.3. MAX® 10 I/O Buffers x
2.3.1. Schmitt-Trigger Input Buffer 2.3.2. Programmable I/O Buffer Features
2.3.2. Programmable I/O Buffer Features x
2.3.2.1. Programmable Open Drain 2.3.2.2. Programmable Bus Hold 2.3.2.3. Programmable Pull-Up Resistor 2.3.2.4. Programmable Current Strength 2.3.2.5. Programmable Output Slew Rate Control 2.3.2.6. Programmable IOE Delay 2.3.2.7. PCI Clamp Diode 2.3.2.8. Programmable Pre-Emphasis 2.3.2.9. Programmable Differential Output Voltage 2.3.2.10. Programmable Emulated Differential Output 2.3.2.11. Programmable Dynamic Power Down
2.4. I/O Standards Termination x
2.4.1. Voltage-Referenced I/O Standards Termination 2.4.2. Differential I/O Standards Termination 2.4.3. MAX® 10 On-Chip I/O Termination
2.4.3. MAX® 10 On-Chip I/O Termination x
2.4.3.1. OCT Calibration 2.4.3.2. RS OCT in MAX® 10 Devices
3. MAX® 10 I/O Design Considerations x
3.1. Guidelines: VCCIO Range Considerations 3.2. Guidelines: Voltage-Referenced I/O Standards Restriction 3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules 3.5. Guidelines: I/O Restriction Rules 3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin 3.7. Guidelines: Analog-to-Digital Converter I/O Restriction 3.8. Guidelines: External Memory Interface I/O Restrictions 3.9. Guidelines: Dual-Purpose Configuration Pin 3.10. Guidelines: Clock and Data Input Signal for MAX® 10 E144 Package 3.11. Guidelines: MultiVolt Input for I/O Banks with 3.3 V, 3.0 V, 1.8 V, or 1.5 V VCCIO 3.12. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610
3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin x
3.6.1. Calculating the Total Inductance for 1.0 V Pin Placement
4. MAX® 10 I/O Implementation Guides x
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP 4.2. Verifying Pin Migration Compatibility 4.3. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP x
4.1.1. GPIO Lite Intel® FPGA IP Data Paths
4.1.1. GPIO Lite Intel® FPGA IP Data Paths x
4.1.1.1. DDR Input Path 4.1.1.2. DDR Output Path with Output Enable
4.3. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 x
4.3.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Parameters 4.3.2. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Analysis 4.3.3. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Mitigation
5. GPIO Lite Intel® FPGA IP References x
5.1. GPIO Lite Intel® FPGA IP Parameter Settings 5.2. GPIO Lite Intel® FPGA IP Interface Signals
1. MAX® 10 I/O Overview
2. MAX® 10 I/O Architecture and Features
3. MAX® 10 I/O Design Considerations
4. MAX® 10 I/O Implementation Guides
5. GPIO Lite Intel® FPGA IP References
6. MAX® 10 General Purpose I/O User Guide Archives
7. Document Revision History for the MAX® 10 General Purpose I/O User Guide

1.1. MAX® 10 Devices I/O Resources Per Package

Table 1.  Package Plan for MAX® 10 Single Power Supply Devices
Device Package
Type

V81

81-pin WLCSP

Y180

180-pin WLCSP

M153

153-pin MBGA

U169

169-pin UBGA

U324

324-pin UBGA

B610

610-pin VPBGA 1

E144

144-pin EQFP

Size 4 mm × 4 mm 6 mm × 5 mm 8 mm × 8 mm 11 mm × 11 mm 15 mm × 15 mm 19 mm × 19 mm 22 mm × 22 mm
Ball Pitch 0.4 mm 0.35 mm 0.5 mm 0.8 mm 0.8 mm Variable 2 0.5 mm
10M02 — — 112 130 246 — 101
10M04 — — 112 130 246 — 101
10M08 58 — 112 130 246 — 101
10M16 — 125 — 130 246 — 101
10M25 — — — — — — 101
10M40 — — — — — 485 101
10M50 — — — — — 485 101
Table 2.  Package Plan for MAX® 10 Dual Power Supply Devices
Device Package
Type

V36

36-pin WLCSP

3

V81

81-pin WLCSP

3

U324

324-pin UBGA

F256

256-pin FBGA

B610

610-pin VPBGA1

F484

484-pin FBGA

F672

672-pin FBGA

Size 3 mm × 3 mm 4 mm × 4 mm 15 mm × 15 mm 17 mm × 17 mm 19 mm × 19 mm 23 mm × 23 mm 27 mm × 27 mm
Ball Pitch 0.4 mm 0.4 mm 0.8 mm 1.0 mm Variable2 1.0 mm 1.0 mm
10M02 27 — 160 — — — —
10M04 — — 246 178 — — —
10M08 — 56 246 178 — 250 —
10M16 — — 246 178 — 320 —
10M25 — — — 178 — 360 —
10M40 — — — 178 485 360 500
10M50 — — — 178 485 360 500
Related Information
1 I/O placement restriction applies. For more information, refer to the MAX® 10 I/O Design Considerations .
2 The Variable Pitch BGA (VPBGA) packaging is compatible with Type III PCBs that use the design rules equivalent to 0.8 mm ball pitch and standard plated through hole (PTH) vias. The VPBGA ball pitch is variable and it helps to ease signal routing. For more information, refer to the MAX® 10 FPGA Signal Integrity Design Guidelines .
3 For the performance specifications of the V36 and V81 packages of MAX® 10 dual power supply devices, follow the data sheet specifications for single supply devices.
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