MAX® 10 General Purpose I/O User Guide

Download PDF
ID 683751
Date 3/17/2025
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 I/O Overview 2. MAX® 10 I/O Architecture and Features 3. MAX® 10 I/O Design Considerations 4. MAX® 10 I/O Implementation Guides 5. GPIO Lite Intel® FPGA IP References 6. MAX® 10 General Purpose I/O User Guide Archives 7. Document Revision History for the MAX® 10 General Purpose I/O User Guide
1. MAX® 10 I/O Overview x
1.1. MAX® 10 Devices I/O Resources Per Package 1.2. MAX® 10 I/O Vertical Migration Support
2. MAX® 10 I/O Architecture and Features x
2.1. MAX® 10 I/O Standards Support 2.2. MAX® 10 I/O Elements 2.3. MAX® 10 I/O Buffers 2.4. I/O Standards Termination
2.1. MAX® 10 I/O Standards Support x
2.1.1. MAX® 10 I/O Standards Voltage and Pin Support
2.2. MAX® 10 I/O Elements x
2.2.1. MAX® 10 I/O Banks Architecture 2.2.2. MAX® 10 I/O Banks Performance 2.2.3. MAX® 10 I/O Banks Locations
2.3. MAX® 10 I/O Buffers x
2.3.1. Schmitt-Trigger Input Buffer 2.3.2. Programmable I/O Buffer Features
2.3.2. Programmable I/O Buffer Features x
2.3.2.1. Programmable Open Drain 2.3.2.2. Programmable Bus Hold 2.3.2.3. Programmable Pull-Up Resistor 2.3.2.4. Programmable Current Strength 2.3.2.5. Programmable Output Slew Rate Control 2.3.2.6. Programmable IOE Delay 2.3.2.7. PCI Clamp Diode 2.3.2.8. Programmable Pre-Emphasis 2.3.2.9. Programmable Differential Output Voltage 2.3.2.10. Programmable Emulated Differential Output 2.3.2.11. Programmable Dynamic Power Down
2.4. I/O Standards Termination x
2.4.1. Voltage-Referenced I/O Standards Termination 2.4.2. Differential I/O Standards Termination 2.4.3. MAX® 10 On-Chip I/O Termination
2.4.3. MAX® 10 On-Chip I/O Termination x
2.4.3.1. OCT Calibration 2.4.3.2. RS OCT in MAX® 10 Devices
3. MAX® 10 I/O Design Considerations x
3.1. Guidelines: VCCIO Range Considerations 3.2. Guidelines: Voltage-Referenced I/O Standards Restriction 3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules 3.5. Guidelines: I/O Restriction Rules 3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin 3.7. Guidelines: Analog-to-Digital Converter I/O Restriction 3.8. Guidelines: External Memory Interface I/O Restrictions 3.9. Guidelines: Dual-Purpose Configuration Pin 3.10. Guidelines: Clock and Data Input Signal for MAX® 10 E144 Package 3.11. Guidelines: MultiVolt Input for I/O Banks with 3.3 V, 3.0 V, 1.8 V, or 1.5 V VCCIO 3.12. Guidelines: LVTTL/LVCMOS I/O Utilization for MAX® 10 FPGA Package B610
3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin x
3.6.1. Calculating the Total Inductance for 1.0 V Pin Placement
4. MAX® 10 I/O Implementation Guides x
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP 4.2. Verifying Pin Migration Compatibility 4.3. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP x
4.1.1. GPIO Lite Intel® FPGA IP Data Paths
4.1.1. GPIO Lite Intel® FPGA IP Data Paths x
4.1.1.1. DDR Input Path 4.1.1.2. DDR Output Path with Output Enable
4.3. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 x
4.3.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Parameters 4.3.2. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Analysis 4.3.3. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Result Mitigation
5. GPIO Lite Intel® FPGA IP References x
5.1. GPIO Lite Intel® FPGA IP Parameter Settings 5.2. GPIO Lite Intel® FPGA IP Interface Signals
1. MAX® 10 I/O Overview
2. MAX® 10 I/O Architecture and Features
3. MAX® 10 I/O Design Considerations
4. MAX® 10 I/O Implementation Guides
5. GPIO Lite Intel® FPGA IP References
6. MAX® 10 General Purpose I/O User Guide Archives
7. Document Revision History for the MAX® 10 General Purpose I/O User Guide

4.3.1. GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Parameters

The GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 has prefilled and non-editable parameters and parameter settings you must specify for the I/O banks you use.
Table 28.   GPIO SSO Estimator Tool for MAX® 10 FPGA Package B610 Parameter Settings
Parameter Allowed Values Description
Board Thickness
  • Thin
  • Thick

Specify the board thickness:

  • Thin—thickness ≤ 65 mil
  • Thick—65 mil < thickness ≤ 125 mil
I/O Bank
  • 1A
  • 1B
  • 2 to 8

This parameter is prefilled and not editable.
Voltage (V)
  • 1
  • 1.2
  • 1.5
  • 1.8
  • 2.5
  • 3
  • 3.3

Specify the voltage for the I/O bank.
Drive Strength
  • 16 mA
  • 12 mA
  • 10 mA
  • 8 mA
  • 6 mA
  • 4 mA
  • 2 mA
  • oct_25
  • oct_50
  • fixed

This parameter is prefilled and not editable.

Note: The "fixed" drive strength setting applies only to the 1.0 V LVCMOS I/O standard. This I/O standard does not support the programmable current strength and OCT features.
IO Standard
  • LVCMOS
  • LVTTL
 Specify the I/O standard for the output.
Slew Rate
  • Slow
  • Medium
  • Fast
 Specify the slew rate setting for the output.
Series Termination (Yes/No)
  • Yes
  • No

Specify whether you want to add a 30 Ω on-board series resistor at the receiver side.

  • Yes—the SSO noise margin calculation considers the series resistor.
  • No—the SSO noise margin calculation does not include the series resistor.
  • Note: Altera recommends that you perform IBIS or SPICE simulations to determine the suitable series resistor value for your specific application.
Toggling Output IO Counts —

Specify the I/O counts of simultaneous toggling output you use in the I/O bank.

Note: By default, this setting is disabled. The setting becomes editable after you set valid values for the other parameters.
Related Information
Level Two Title