PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/10/2023
Public

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Document Table of Contents

5.7.1. Implementation using the PHY Lite for Parallel Interfaces IP

You can configure the PHY Lite for Parallel Interfaces IP to support multiple groups (maximum 48 I/O pins each).

The following lists the possible implementations:

  • Instantiates one PHY Lite for Parallel Interfaces IP with two groups
    • Bidirectional type for DQ and DQS signals
    • Output type for Addr/Cmd signals
Note: Each group in the PHY Lite for Parallel Interfaces IP can have 48 I/Os, and the IP supports up to 18 groups.
Figure 105.  General Tab Settings


Figure 106.  Group 0 settings (Bidirectional type for DQ and DQS)


Figure 107.  Group 1 settings (Output type for Addr/Cmd)