PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.2.5.3.2. Control Registers Description

When you generate a read operation to the control registers addresses, the Avalon interface returns a set of values from the control registers. The following tables show the definition of the bits for each control register.
Table 58.  Control Register Description
Feature Bit Description
Pin Output Delay [31:13]

Reserved 9

[12:0]

Phase value

Strobe minimum setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.

Strobe maximum setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.

Incremental Delay: 1/128th VCO clock period

The CSR value for DQS is set through the Output Strobe Phase parameter during IP instantiation.

Note: The pin output delay switches from the CSR register value to the Avalon register value after the first Avalon write. It is only reset to the CSR register value on a reset of the interface.
Pin Input Delay [31:13]

Reserved 9

[12]

Enable bit to select access to Avalon register or CSR register.

0 = Delay value is 0. CSR register is not available for this feature.

1 = Select delay value from Avalon register

[11:9] Reserved 9
[8:0]

Delay value

Minimum Setting: 0

Maximum Setting: 511 VCO clock periods

Incremental Delay: 1/256th VCO clock period

Strobe Input Delay [31:13]

Reserved 9

[12]

Enable bit to select access to Avalon register or CSR register.

0 = Delay value is 0. CSR register is not available for this feature.

1 = Select delay value from Avalon register

Modifying these values must be done on all lanes in a group.

[11:10] Reserved9
[9:0]

Delay value

Minimum Setting: 0

Maximum Setting: 1023 VCO clock periods

Incremental Delay: 1/256th VCO clock period

Modifying these values must be done on all lanes in a group.

Strobe Enable Phase [31:16] Reserved 9
[15]

Enable bit to select access to Avalon register or CSR register.

0 = Select delay value from CSR register. The CSR value is set through the Capture Strobe Phase Shift parameter during IP instantiation.

1 = Select delay value from Avalon register

Modifying these values must be done on all lanes in a group.

[14:13] Reserved9
[12:0]

Bit [12:0]: Phase value

Minimum Setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.

Maximum Setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.

Incremental Delay: 1/128th VCO clock period

Modifying these values must be done on all lanes in a group.

Strobe Enable Delay [31:16] Reserved9
[15]

Enable bit to select access to Avalon register or CSR register.

0 = Select delay value from CSR register

1 = Select delay value from Avalon register

Modifying these values must be done on all lanes in a group.

[14:6] Reserved9
[5:0]

Delay value

Minimum Setting: 0 external clock cycles

Maximum Setting: 63 external memory clock cycles

Incremental Delay: 1 external memory clock cycle

Modifying these values must be done on all lanes in a group.

Read Valid Delay [31:16] Reserved9
[15]

Enable bit to select access to Avalon register or CSR register.

0 = Select delay value from CSR register

1 = Select delay value from Avalon register

Modifying these values must be done on all lanes in a group.

[14:7] Reserved
[6:0]

Delay value

Minimum Setting: 0 external clock cycles

Maximum Setting: 127 external memory clock cycles

Incremental Delay: 1 external memory clock cycle

Modifying these values must be done on all lanes in a group.

Important: For more information about performing various clocking and delay calculations, depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.

Example of Accessing Dynamic Reconfiguration Control Registers using Parameter Table

The example shows the steps to access Pin Output Delay CSR control register for a strobe pin with the following PHY Lite for Parallel Interfaces IP settings in Intel® Stratix® 10 devices:
  • Number of groups: 2. The group index is automatically set to 0x00.
  • Interface ID: 0x00
  • Pin width: 4
  • Strobe configuration: Single ended
  • Avalon controller calibration bus base address: 0x3000000
After the project compilation, the interface ID, lane address and pin addresses are stored in the parameter table.
The Pin Output Delay CSR control register has the following bit definition:
Bit Description Avalon® MM Register Value
[30:27] Specify the PHY Lite for Parallel Interfaces IP interface ID.

0x00 (Interface ID from parameter table)

[26:24] Specify the Avalon controller calibration bus base address. 0x3
[23:21] Reserved 0x00
[20:13] Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. 0x4b (Lane address from parameter table)
[12:8] Specify the address for the physical location of a pin within a lane. 0x04 (Strobe pin address from parameter table)
[7:0] Reserved 0xe8
To read the Pin Output Delay CSR control register for a strobe pin, use the command
avl_in_address[30:0] = {interface id[30:27], calibration bus address[26:24], Reserved[23:21], lanes address[20:13], pin address[12:8], reserved[7:0]}
avl_in_address[30:0] = {0x00, 0x3, 0x00, 0x4B, 0x04, 0xE8}
9 Reserved bit ranges must be zero