PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/10/2023
Public

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2.2.1.1. Clocks

The PHY Lite for Parallel Interfaces for Intel® Agilex™ M-Series IP uses a reference clock that is sourced from a dedicated clock pin to the PLL inside the IP. This PLL provides four clock domains for the output and input paths.
Table 2.   PHY Lite for Parallel Interfaces for Intel® Agilex™ M-Series IP Clock Domains
Clock Domain Description
Core clock This clock is generated internally by the IP and is used for all transfers between the FPGA core fabric and I/O banks. The clock phase alignment (CPA) circuitry ensures that this clock is kept in phase with the PHY clock for core-to-periphery and periphery-to-core transfers.
PHY clock This clock is used internally by the IP for PHY circuitry.
VCO clock This clock is generated internally by the PLL. It is used by both the input and output paths to generate PVT compensated delays in the interpolator.
Interface clock This is the clock frequency of the external device connected to the FPGA I/Os.
Table 3.   PHY Lite for Parallel Interfaces for Intel® Agilex™ M-Series IP Supported Interface Frequency
Interface Frequency (MHz) Core Clock Rate (PHYLITE_IN_RATE) VCO Frequency Multiplier Factor (PHYLITE_OUT_RATE) VCO Clock Frequency (MHz) PHY Clock (MHz) Core Clock Frequency (MHz)
600-1250 4 1 600-1250 300-625 150-312.5
300-600 2 2 600-1200 300-600 150-300
150-300 1 4 600-1200 300-600 150-300
Note: The core clock rate of the PHY Lite for Parallel Interfaces IP is fixed based on selected interface frequency.