Visible to Intel only — GUID: gkc1599793583629
Ixiasoft
Visible to Intel only — GUID: gkc1599793583629
Ixiasoft
4.3.2.4. Avalon Configuration Bus Interface Signals
The PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP exposes the Avalon memory-mapped-MM slave and Avalon memory-mapped master interfaces when you perform dynamic reconfiguration. Connect the Avalon memory-mapped slave to either a master in the core or the master interface of either an PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP or the External Memory Interface IP to be placed in the same column. You can only connect the master interface to the slave interface of a PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP or External Memory Interface IP to be placed in the same column.
Signal Name | Direction | Width | Description |
---|---|---|---|
avl_clk | Input | 1 | Avalon interface clock. Maximum Avalon memory-mapped interface clock for PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP is 167 MHz. |
avl_reset_n | Input | 1 | Reset input synchronous to avl_clk. |
avl_read | Input | 1 | Read request from io_aux. This signal is synchronous to the avl_clk input. |
avl_write | Input | 1 | Write request from io_aux. This signal is synchronous to the avl_clk input. |
avl_byteenable | Input | 4 | Controls which bytes should be written on avl_writedata. |
avl_address | Input | 31 |
Address from io_aux. This signal is synchronous to the avl_clk input. |
avl_readdata | Output | 32 | Read data to io_aux. This signal is synchronous to the avl_clk input. |
avl_writedata | Input | 32 | Write data from io_aux. This signal is synchronous to the avl_clk input. |
avl_readdata_valid | Output | 1 | Indicates that read data has returned. |
avl_waitrequest | Output | 1 | Stalls upstream logic when it is asserted. |
Signal Name | Direction | Width | Description |
---|---|---|---|
avl_out_clk | Output | 1 | Connect this signal to the input Avalon interface of another PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP or the External Memory Interfaces IP. |
avl_out_reset_n | Output | 1 | Connect this signal to the input Avalon interface of another PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP or the External Memory Interfaces IP. |
avl_out_read | Output | 1 | Indicates read transaction. |
avl_out_write | Output | 1 | Indicates write transaction. |
avl_out_byteenable | Output | 4 | Controls which bytes should be written on avl_out_writedata. |
avl_out_writedata | Output | 32 | The data packet associated with the write transaction. |
avl_out_address | Output | 31 |
Avalon address (in byte granularity). Value is identical to avl_address but with zeroes padded on the LSBs. |
avl_out_readdata | Input | 32 | The data packet associated with avl_out_readdata_valid. |
avl_out_readdata_valid | Input | 1 | Indicates that read data has returned. |
avl_out_waitrequest | Input | 1 | Stalls upstream logic when it is asserted. |