Cyclone® V Device Overview

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ID 683694
Date 5/07/2018
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Overview
Cyclone V Device Overview x
Key Advantages of Cyclone® V Devices Summary of Cyclone® V Features Cyclone® V Device Variants and Packages I/O Vertical Migration for Cyclone® V Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O PCIe* Gen1 and Gen2 Hard IP External Memory Interface Low-Power Serial Transceivers SoC with HPS Dynamic Reconfiguration Enhanced Configuration and Configuration via Protocol Power Management Document Revision History for Cyclone® V Device Overview
Cyclone® V Device Variants and Packages x
Cyclone® V E Cyclone® V GX Cyclone® V GT Cyclone® V SE Cyclone® V SX Cyclone® V ST
Cyclone® V E x
Available Options Maximum Resources Package Plan
Cyclone® V GX x
Available Options Maximum Resources Package Plan
Cyclone® V GT x
Available Options Maximum Resources Package Plan
Cyclone® V SE x
Available Options Maximum Resources Package Plan
Cyclone® V SX x
Available Options Maximum Resources Package Plan
Cyclone® V ST x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Cyclone V Devices Embedded Memory Configurations
External Memory Interface x
Hard and Soft Memory Controllers External Memory Performance HPS External Memory Performance
Low-Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
SoC with HPS x
HPS Features FPGA Configuration and Processor Booting Hardware and Software Development
HPS Features x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Cyclone V Device Overview

Package Plan

Table 15.  Package Plan for Cyclone® V ST Devices
  • The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.
  • Transceiver counts shown are for transceiver ≤5 Gbps . 6 Gbps transceiver channel count support depends on the package and channel usage. For more information about the 6 Gbps transceiver channel count, refer to the Cyclone® V Device Handbook Volume 2: Transceivers.
Member Code

F896

(31 mm)

FPGA GPIO HPS I/O XCVR
D5 288 181 9 11
D6 288 181 9 11
Related Information
11 If you require CPRI (at 4.9152 Gbps) and PCIe Gen2 transmit jitter compliance, Intel recommends that you use only up to seven full-duplex transceiver channels for CPRI, and up to six full-duplex channels for PCIe Gen2. The CMU channels are not considered full-duplex channels.
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