Cyclone® V Device Overview

Download PDF
ID 683694
Date 5/07/2018
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Overview
Cyclone V Device Overview x
Key Advantages of Cyclone® V Devices Summary of Cyclone® V Features Cyclone® V Device Variants and Packages I/O Vertical Migration for Cyclone® V Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O PCIe* Gen1 and Gen2 Hard IP External Memory Interface Low-Power Serial Transceivers SoC with HPS Dynamic Reconfiguration Enhanced Configuration and Configuration via Protocol Power Management Document Revision History for Cyclone® V Device Overview
Cyclone® V Device Variants and Packages x
Cyclone® V E Cyclone® V GX Cyclone® V GT Cyclone® V SE Cyclone® V SX Cyclone® V ST
Cyclone® V E x
Available Options Maximum Resources Package Plan
Cyclone® V GX x
Available Options Maximum Resources Package Plan
Cyclone® V GT x
Available Options Maximum Resources Package Plan
Cyclone® V SE x
Available Options Maximum Resources Package Plan
Cyclone® V SX x
Available Options Maximum Resources Package Plan
Cyclone® V ST x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Cyclone V Devices Embedded Memory Configurations
External Memory Interface x
Hard and Soft Memory Controllers External Memory Performance HPS External Memory Performance
Low-Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
SoC with HPS x
HPS Features FPGA Configuration and Processor Booting Hardware and Software Development
HPS Features x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Cyclone V Device Overview

PCIe* Gen1 and Gen2 Hard IP

Cyclone® V GX, GT, SX, and ST devices contain PCIe* hard IP that is designed for performance and ease-of-use. The PCIe* hard IP consists of the MAC, data link, and transaction layers.

The PCIe* hard IP supports PCIe* Gen2 and Gen1 end point and root port for up to x4 lane configuration. The PCIe* Gen2 x4 support is PCIe* -compatible.

The PCIe* endpoint support includes multifunction support for up to eight functions, as shown in the following figure. The integrated multifunction support reduces the FPGA logic requirements by up to 20,000 LEs for PCIe* designs that require multiple peripherals.

Figure 9.  PCIe* Multifunction for Cyclone® V Devices


The Cyclone® V PCIe* hard IP operates independently from the core logic. This independent operation allows the PCIe* link to wake up and complete link training in less than 100 ms while the Cyclone® V device completes loading the programming file for the rest of the device.

In addition, the PCIe* hard IP in the Cyclone® V device provides improved end-to-end datapath protection using ECC.

Level Two Title