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Ixiasoft
Key Advantages of Cyclone® V Devices
Summary of Cyclone® V Features
Cyclone® V Device Variants and Packages
I/O Vertical Migration for Cyclone® V Devices
Adaptive Logic Module
Variable-Precision DSP Block
Embedded Memory Blocks
Clock Networks and PLL Clock Sources
FPGA General Purpose I/O
PCIe* Gen1 and Gen2 Hard IP
External Memory Interface
Low-Power Serial Transceivers
SoC with HPS
Dynamic Reconfiguration
Enhanced Configuration and Configuration via Protocol
Power Management
Document Revision History for Cyclone® V Device Overview
Visible to Intel only — GUID: sam1403480304257
Ixiasoft
Maximum Resources
Resource | Member Code | |||||
---|---|---|---|---|---|---|
A2 | A4 | A5 | A7 | A9 | ||
Logic Elements (LE) (K) | 25 | 49 | 77 | 150 | 301 | |
ALM | 9,430 | 18,480 | 29,080 | 56,480 | 113,560 | |
Register | 37,736 | 73,920 | 116,320 | 225,920 | 454,240 | |
Memory (Kb) | M10K | 1,760 | 3,080 | 4,460 | 6,860 | 12,200 |
MLAB | 196 | 303 | 424 | 836 | 1,717 | |
Variable-precision DSP Block | 25 | 66 | 150 | 156 | 342 | |
18 x 18 Multiplier | 50 | 132 | 300 | 312 | 684 | |
PLL | 4 | 4 | 6 | 7 | 8 | |
GPIO | 224 | 224 | 240 | 480 | 480 | |
LVDS | Transmitter | 56 | 56 | 60 | 120 | 120 |
Receiver | 56 | 56 | 60 | 120 | 120 | |
Hard Memory Controller | 1 | 1 | 2 | 2 | 2 |
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