Cyclone® V Device Overview

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ID 683694
Date 5/07/2018
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Overview
Cyclone V Device Overview x
Key Advantages of Cyclone® V Devices Summary of Cyclone® V Features Cyclone® V Device Variants and Packages I/O Vertical Migration for Cyclone® V Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O PCIe* Gen1 and Gen2 Hard IP External Memory Interface Low-Power Serial Transceivers SoC with HPS Dynamic Reconfiguration Enhanced Configuration and Configuration via Protocol Power Management Document Revision History for Cyclone® V Device Overview
Cyclone® V Device Variants and Packages x
Cyclone® V E Cyclone® V GX Cyclone® V GT Cyclone® V SE Cyclone® V SX Cyclone® V ST
Cyclone® V E x
Available Options Maximum Resources Package Plan
Cyclone® V GX x
Available Options Maximum Resources Package Plan
Cyclone® V GT x
Available Options Maximum Resources Package Plan
Cyclone® V SE x
Available Options Maximum Resources Package Plan
Cyclone® V SX x
Available Options Maximum Resources Package Plan
Cyclone® V ST x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Cyclone V Devices Embedded Memory Configurations
External Memory Interface x
Hard and Soft Memory Controllers External Memory Performance HPS External Memory Performance
Low-Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
SoC with HPS x
HPS Features FPGA Configuration and Processor Booting Hardware and Software Development
HPS Features x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Cyclone V Device Overview

Document Revision History for Cyclone® V Device Overview

Document Version Changes
2018.05.07
  • Added the low power option ("L" suffix) for Cyclone® V SE and Cyclone® V SX devices in the Sample Ordering Code and Available Options diagrams.
  • Rebranded as Intel.
Date Version Changes
December 2017 2017.12.18
  • Updated ALM resources for Cyclone V E, Cyclone V SE, Cyclone V SX, and Cyclone V ST devices.
June 2016 2016.06.10 Updated Cyclone® V GT speed grade to –7 in Sample Ordering Code and Available Options for Cyclone® V GT Devices diagram.
December 2015 2015.12.21
  • Added descriptions to package plan tables for Cyclone® V GT and ST devices.
  • Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.12
  • Replaced a note to partial reconfiguration feature. Note: The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices with the "SC" suffix in the part number. For device availability and ordering, contact your local Altera sales representatives.
  • Updated logic elements (LE) (K) for the following devices:
    • Cyclone® V E A7: Updated from 149.5 to 150
    • Cyclone® V GX C3: Updated from 35.5 to 36
    • Cyclone® V GX C7: Updated from 149.7 to 150
    • Cyclone® V GT D7: Updated from 149.5 to 150
  • Updated MLAB (Kb) in Maximum Resource Counts for Cyclone V GX Devices table as follows:
    • Cyclone® V GX C3: Updated from 291 to 182
    • Cyclone® V GX C4: Updated from 678 to 424
    • Cyclone® V GX C5: Updated from 678 to 424
    • Cyclone® V GX C7: Updated from 1,338 to 836
    • Cyclone® V GX C9: Updated from 2,748 to 1,717
  • Updated MLAB RAM Bit (Kb) in Embedded Memory Capacity and Distribution in Cyclone V Devices table as follows:
    • Cyclone® V GX C3: Updated from 181 to 182
    • Cyclone® V GX C4: Updated from 295 to 424
  • Updated Total RAM Bit (Kb) in Embedded Memory Capacity and Distribution in Cyclone V Devices table as follows:
    • Cyclone® V GX C3: Updated from 1,531 to 1,532
    • Cyclone® V GX C4: Updated from 2,795 to 2,924
  • Updated MLAB Block count in Embedded Memory Capacity and Distribution in Cyclone V Devices table as follows:
    • Cyclone® V GX C4: Updated from 472 to 678
    • Cyclone® V GX C5: Updated from 679 to 678
March 2015 2015.03.31
  • Added internal scrubbing feature under configuration in Summary of Features for Cyclone® V Devices table.
  • Added optional suffix "SC: Internal scrubbing support" to the following diagrams:
    • Sample Ordering Code and Available Options for Cyclone® V E Devices
    • Sample Ordering Code and Available Options for Cyclone® V GX Devices
    • Sample Ordering Code and Available Options for Cyclone® V SE Devices
    • Sample Ordering Code and Available Options for Cyclone® V SX Devices
January 2015 2015.01.23
  • Updated Sample Ordering Code and Available Options for Cyclone® V ST Devices figure because Cyclone® V ST devices are only available in I temperature grade and –7 speed grade.
    • Operating Temperature: Removed C and A temperature grades
    • FPGA Fabric Speed Grade: Removed –6 and –8 speed grades
  • Updated the transceiver specification for Cyclone® V ST from 5 Gbps to 6.144 Gbps:
    • Device Variants for the Cyclone® V Device Family table
    • Sample Ordering Code and Available Options for Cyclone® V ST Devices figure
    • Maximum Resource Counts for Cyclone V ST Devices
  • Updated Maximum Resource Counts for Cyclone® V GX Devices table for Cyclone® V GX G3 devices.
    • Logic elements (LE) (K): Updated from 35.7 to 35.5
    • Variable-precision DSP block: Updated from 51 to 57
    • 18 x 18 multiplier: Updated from 102 to 114
  • Updated Number of Multipliers in Cyclone® V Devices table for Cyclone® V GX G3 devices.
    • Variable-precision DSP Block: Updated from 51 to 57
    • 9 x 9 Multiplier: Updated from 153 to 171
    • 18 x 18 Multiplier: Updated from 102 to 114
    • 27 x 27 Multiplier: Updated from 51 to 57
    • 18 x 18 Multiplier Adder Mode: Updated from 51 to 57
    • 18 x 18 Multiplier Adder Summed with 36 bit Input: Updated from 51 to 57
  • Updated Embedded Memory Capacity and Distribution in Cyclone V Devices table for Cyclone® V GX G3 devices.
    • M10K block: Updated from 119 to 135
    • M10K RAM bit (Kb): Updated from 1,190 to 1,350
    • MLAB block: Updated from 255 to 291
    • MLAB RAM bit (Kb): Updated from 159 to 181
    • Total RAM bit (Kb): Updated from 1,349 to 1,531
October 2014 2014.10.06 Added a footnote to the "Transceiver PCS Features for Cyclone® V Devices" table to show that PCIe Gen2 is supported for Cyclone V GT and ST devices.
July 2014 2014.07.07

Updated the I/O vertical migration figure to clarify the migration capability of Cyclone® V SE and SX devices.

December 2013 2013.12.26
  • Corrected single or dual-core ARM Cortex-A9 MPCore processor-up to 925 MHz from 800 MHz.
  • Removed "Preliminary" texts from Ordering Code figures, Maximum Resources, Package Plan and I/O Vertical Migration tables.
  • Removed the note "The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os includes transceiver I/Os." for GPIOs in the Maximum Resource Counts table for Cyclone® V E and SE.
  • Added link to Altera Product Selector for each device variant.
  • Updated Embedded Hard IPs for Cyclone® V GT devices to indicate Maximum 2 hard PCIe and 2 hard memory controllers.
  • Added leaded package options.
  • Removed the note "The number of PLLs includes general-purpose fractional PLLs and transceiver fractional PLLs." for all PLLs in the Maximum Resource Counts table.
  • Corrected max LVDS counts for transmitter and receiver for Cyclone® V E A5 device from 84 to 60.
  • Corrected max LVDS counts for transmitter and receiver for Cyclone® V E A9 device from 140 to 120.
  • Corrected variable-precision DSP block, 27 x 27 multiplier, 18 x 18 multiplier adder mode and 18 x 18 multiplier adder summed with 36 bit input for Cyclone® V SE devices from 58 to 84.
  • Corrected 18 x 18 multiplier for Cyclone® V SE devices from 116 to 168.
  • Corrected 9 x 9 multiplier for Cyclone® V SE devices from 174 to 252.
  • Corrected LVDS transmitter for Cyclone® V SE A2 and A4 as well as SX C2 and C4 devices from 31 to 32.
  • Corrected LVDS receiver for Cyclone® V SE A2 and A4 as well as SX C2 and C4 devices from 35 to 37.
  • Corrected transceiver speed grade for Cyclone® V ST devices ordering code from 4 to 5.
  • Updated the DDR3 SDRAM for the maximum frequency's soft controller and the minimum frequency from 300 to 303 for voltage 1.35V.
  • Added links to Altera's External Memory Spec Estimator tool to the topics listing the external memory interface performance.
  • Corrected XAUI is supported through the soft PCS in the PCS features for Cyclone® V.
  • Added decompression support for the CvP configuration mode.
May 2013 2013.05.06
  • Added link to the known document issues in the Knowledge Base.
  • Moved all links to the Related Information section of respective topics for easy reference.
  • Corrected the title to the PCIe hard IP topic. Cyclone® V devices support only PCIe Gen1 and Gen2.
  • Updated Supporting Feature in Table 1 of Increased bandwidth capacity to '6.144 Gbps'.
  • Updated Description in Table 2 of Low-power high-speed serial interface to '6.144 Gbps'.
  • Updated Description in Table 3 of Cyclone® V GT to '6.144 Gbps'.
  • Updated the M386 package to M383 for Figure 1, Figure 2 and Figure 3.
  • Updated Figure 2 and Figure 3 for Transceiver Count by adding 'F : 4'.
  • Updated LVDS in the Maximum Resource Counts tables to include Transmitter and Receiver values.
  • Updated the package plan with M383 for the Cyclone® V E device.
  • Removed the M301 and M383 packages from the Cyclone® V GX C4 device.
  • Updated the GPIO count to '129' for the M301 package of the Cyclone® V GX C5 device.
  • Updated 5 Gbps to '6.144 Gbps' for Cyclone® V GT device.
  • Updated HPS I/O for U484 (19 mm) in Table 11 with '151' for A2, A4, A5 and A6.
  • Updated Memory (Kb) for Maximum Resource Counts for Cyclone® V SE A4 and A6, SX C4 and C6, ST D6 devices.
  • Updated FPGA PLL for Maximum Resource Counts for Cyclone® V SE A2, SX C2, devices.
  • Removed '36 x 36' from the Variable-Precision DSP Block.
  • Updated Variable-precision DSP Blocks and 18 x 18 Multiplier for Maximum Resource Counts for Cyclone® V SX C4 device.
  • Updated the HPS I/O counts for Cyclone® V SE, SX, and ST devices.
  • Updated Figure 7 which shows the I/O vertical migration table.
  • Updated Table 17 for Cyclone® V SX C4 device.
  • Updated Embedded Memory Capacity and Distribution table for Cyclone® V SE A4 and A6, SX C4 and C6, ST D6 devices.
  • Removed 'Counter reconfiguration' from the PLL Features.
  • Updated Low-Power Serial Transceivers by replacing 5 Gbps with 6.144 Gbps.
  • Removed 'Distributed Memory' symbol.
  • Updated the Capability in Table 22 of Backplane support to '6.144 Gbps'.
  • Updated Capability in Table 22 of Ring oscillator transmit PLLs with 6.144 Gbps.
  • Updated the PCS Support in Table 23 from 5 Gbps to '6 Gbps'.
  • Updated the Data Rates (Gbps) in Table 23 of 3 Gbps and 6 Gbps Basic to '6.144 Gbps'.
  • Updated the Data Rates (Gbps) in Table 23 of CPRI 4.1 to '6.144 Gbps'.
  • Clarified that partial reconfiguration is an advanced feature. Contact Altera for support of the feature.
December 2012 2012.12.28
  • Updated the pin counts for the MBGA packages.
  • Updated the GPIO and transceiver counts for the MBGA packages.
  • Updated the GPIO counts for the U484 package of the Cyclone V E A9, GX C9, and GT D9 devices.
  • Updated the vertical migration table for vertical migration of the U484 packages.
  • Updated the MLAB supported programmable widths at 32 bits depth.
November 2012 2012.11.19
  • Added new MBGA packages and additional U484 packages for Cyclone V E, GX, and GT.
  • Added ordering code for five-transceiver devices for Cyclone V GT and ST.
  • Updated the vertical migration table to add MBGA packages.
  • Added performance information for HPS memory controller.
  • Removed DDR3U support.
  • Updated Cyclone V ST speed grade information.
  • Added information on maximum transceiver channel usage restrictions for PCI Gen2 and CPRI at 4.9152 Gbps transmit jitter compliance.
  • Added note on the differences between GPIO reported in Overview with User I/O numbers shown in the Quartus II software.
  • Updated template.
July 2012 2.1 Added support for PCIe Gen2 x4 lane configuration (PCIe-compatible)
June 2012 2.0
  • Restructured the document.
  • Added the “Embedded Memory Capacity” and “Embedded Memory Configurations” sections.
  • Added Table 1, Table 3, Table 16, Table 19, and Table 20.
  • Updated Table 2, Table 4, Table 5, Table 6, Table 7, Table 8, Table 9, Table 10, Table 11, Table 12, Table 13, Table 14, Table 17, and Table 18.
  • Updated Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, and Figure 10.
  • Updated the “FPGA Configuration and Processor Booting” and “Hardware and Software Development” sections.
  • Text edits throughout the document.
February 2012 1.2
  • Updated Table 1–2, Table 1–3, and Table 1–6.
  • Updated “Cyclone V Family Plan” on page 1–4 and “Clock Networks and PLL Clock Sources” on page 1–15.
  • Updated Figure 1–1 and Figure 1–6.
November 2011 1.1
  • Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, Table 1–5, and Table 1–6.
  • Updated Figure 1–4, Figure 1–5, Figure 1–6, Figure 1–7, and Figure 1–8.
  • Updated “System Peripherals” on page 1–18, “HPS–FPGA AXI Bridges” on page 1–19, “HPS SDRAM Controller Subsystem” on page 1–19, “FPGA Configuration and Processor Booting” on page 1–19, and “Hardware and Software Development” on page 1–20.
  • Minor text edits.
October 2011 1.0 Initial release.
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