Cyclone® V Device Overview

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ID 683694
Date 5/07/2018
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Overview
Cyclone V Device Overview x
Key Advantages of Cyclone® V Devices Summary of Cyclone® V Features Cyclone® V Device Variants and Packages I/O Vertical Migration for Cyclone® V Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O PCIe* Gen1 and Gen2 Hard IP External Memory Interface Low-Power Serial Transceivers SoC with HPS Dynamic Reconfiguration Enhanced Configuration and Configuration via Protocol Power Management Document Revision History for Cyclone® V Device Overview
Cyclone® V Device Variants and Packages x
Cyclone® V E Cyclone® V GX Cyclone® V GT Cyclone® V SE Cyclone® V SX Cyclone® V ST
Cyclone® V E x
Available Options Maximum Resources Package Plan
Cyclone® V GX x
Available Options Maximum Resources Package Plan
Cyclone® V GT x
Available Options Maximum Resources Package Plan
Cyclone® V SE x
Available Options Maximum Resources Package Plan
Cyclone® V SX x
Available Options Maximum Resources Package Plan
Cyclone® V ST x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Cyclone V Devices Embedded Memory Configurations
External Memory Interface x
Hard and Soft Memory Controllers External Memory Performance HPS External Memory Performance
Low-Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
SoC with HPS x
HPS Features FPGA Configuration and Processor Booting Hardware and Software Development
HPS Features x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Cyclone V Device Overview

Maximum Resources

Table 12.  Maximum Resource Counts for Cyclone V SX Devices
Resource Member Code
C2 C4 C5 C6
Logic Elements (LE) (K) 25 40 85 110
ALM 9,430 15,880 32,070 41,910
Register 37,736 60,376 128,300 166,036
Memory (Kb) M10K 1,400 2,700 3,970 5,570
MLAB 138 231 480 621
Variable-precision DSP Block 36 84 87 112
18 x 18 Multiplier 72 168 174 224
FPGA PLL 5 5 6 6
HPS PLL 3 3 3 3
3 Gbps Transceiver 6 6 9 9
FPGA GPIO 8 145 145 288 288
HPS I/O 181 181 181 181
LVDS Transmitter 32 32 72 72
Receiver 37 37 72 72
PCIe* Hard IP Block 2 2 2 9 2 9
FPGA Hard Memory Controller 1 1 1 1
HPS Hard Memory Controller 1 1 1 1
Arm* Cortex* -A9 MPCore* Processor Dual-core Dual-core Dual-core Dual-core
Related Information
8 The number of GPIOs does not include transceiver I/Os. In the Intel® Quartus® Prime software, the number of user I/Os includes transceiver I/Os.
9 1 PCIe Hard IP Block in U672 package.
Level Two Title