AN 954: Hierarchical Partial Reconfiguration Tutorial: for the Intel® Agilex® F-Series FPGA Development Board

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ID 683687
Date 8/04/2021
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Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for the Intel® Agilex® F-Series FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for the Intel® Agilex® F-Series FPGA Development Board x
Reference Design Overview Reference Design Requirements Reference Design Files Reference Design Walkthrough Document Revision History for AN 954: Hierarchical Partial Reconfiguration Tutorial for Intel® Agilex® F-Series FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Submodule Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing the PR Implementation Revisions for Parent PR Partition Step 9: Preparing the PR Implementation Revisions for Child PR Partitions Step 10: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 10: Programming the Board x
Programming the Child PR Region
Hierarchical Partial Reconfiguration Tutorial for the Intel® Agilex® F-Series FPGA Development Board

Step 3: Creating Design Partitions

You must create design partitions for each PR region that you want to partially reconfigure. You can create any number of independent partitions or PR regions in your design. This tutorial creates two design partitions for the u_blinking_led_child and u_blinking_led instances.
To create design partitions for hierarchical partial reconfiguration:
  1. Right-click the u_blinking_led_child instance in the Project Navigator and click Design Partition > Reconfigurable.
    Figure 3. Create Design Partition
  2. Click Assignments > Design Partitions Window. The window displays all design partitions in the project.
  3. Edit the default partition name in the Design Partitions Window by double-clicking the name. Rename the partition to pr_partition.
  4. Repeat steps 1 and 2 to assign reconfigurable design partitions to the u_blinking_led instance. Rename this partition to pr_parent_partition.
  5. In the Design Partitions Window, click (…) at the farthest right column header and enable the Post Final Export File column.
  6. To export the finalized static region from the base revision compile, double-click the entry for root_partition in the Post Final Export File column, and type blinking_led_static.qdb. This file is for the subsequent PR implementation compiles.
  7. To export the finalized parent PR partition from the base revision compile, double-click the entry for pr_parent_partition in Post Final Export File, and type pr_parent_partition_default_final.qdb. This file is for the subsequent PR implementation compiles.
Figure 4. Design Partitions Window
Verify that the blinking_led.qsf contains the following assignments, corresponding to your reconfigurable design partitions: 
set_instance_assignment -name PARTITION pr_partition -to \
        u_blinking_led|u_blinking_led_child
set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to \
        u_blinking_led|u_blinking_led_child
set_instance_assignment -name PARTITION pr_parent_partition -to \
        u_blinking_led
set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to \
        u_blinking_led
set_instance_assignment -name EXPORT_PARTITION_SNAPSHOT_FINAL \	
        blinking_led_static.qdb -to | -entity top
set_instance_assignment -name EXPORT_PARTITION_SNAPSHOT_FINAL \ 	
        pr_parent_partition_default_final.qdb -to u_blinking_led -entity top
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