Visible to Intel only — GUID: dpy1623773193396
Ixiasoft
Step 1: Getting Started
Step 2: Creating a Child Level Submodule
Step 3: Creating Design Partitions
Step 4: Allocating Placement and Routing Region for PR Partitions
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing the PR Implementation Revisions for Parent PR Partition
Step 9: Preparing the PR Implementation Revisions for Child PR Partitions
Step 10: Programming the Board
Modifying an Existing Persona
Adding a New Persona to the Design
Visible to Intel only — GUID: dpy1623773193396
Ixiasoft
Step 2: Creating a Child Level Submodule
To convert the flat design into a hierarchical PR design, you create a child submodule (blinking_led_child.sv) within the parent submodule (blinking_led.sv).
- Create a new design file, blinking_led_child.sv, and add the following lines of code to this file:
`timescale 1 ps / 1 ps `default_nettype none module blinking_led_child ( // clock input wire clock, input wire [31:0] counter, // Control signals for the LEDs output wire led_three_on ); localparam COUNTER_TAP = 23; reg led_three_on_r; assign led_three_on = led_three_on_r; always_ff @(posedge clock) begin led_three_on_r <= counter[COUNTER_TAP]; end endmodule
- Modify blinking_led.sv to connect led_two_on to bit 23 of the counter from the static region, and instantiate the blinking_led_child module. blinking_led.sv must appear as follows:
`timescale 1 ps / 1 ps `default_nettype none module blinking_led( // clock input wire clock, input wire [31:0] counter, // Control signals for the LEDs output wire led_two_on, output wire led_three_on ); localparam COUNTER_TAP = 23; reg led_two_on_r; assign led_two_on = led_two_on_r; // The counter: always_ff @(posedge clock) begin led_two_on_r <= counter[COUNTER_TAP]; end blinking_led_child u_blinking_led_child ( .led_three_on (led_three_on), .counter (counter), .clock (clock) ); endmodule
- Save all files, retaining the Add file to current project option.
- Click Processing > Start > Start Analysis & Synthesis