AN 954: Hierarchical Partial Reconfiguration Tutorial: for the Intel® Agilex® F-Series FPGA Development Board

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ID 683687
Date 8/04/2021
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Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for the Intel® Agilex® F-Series FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for the Intel® Agilex® F-Series FPGA Development Board x
Reference Design Overview Reference Design Requirements Reference Design Files Reference Design Walkthrough Document Revision History for AN 954: Hierarchical Partial Reconfiguration Tutorial for Intel® Agilex® F-Series FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Submodule Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing the PR Implementation Revisions for Parent PR Partition Step 9: Preparing the PR Implementation Revisions for Child PR Partitions Step 10: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 10: Programming the Board x
Programming the Child PR Region
Hierarchical Partial Reconfiguration Tutorial for the Intel® Agilex® F-Series FPGA Development Board

Programming the Child PR Region

The current version of the Intel® Quartus® Prime Pro Edition software does not provide a mechanism to check for incompatible child PR bitstreams for Intel® Agilex® devices. So, it is very important that you program the correct child persona to match the parent persona.
Programming an incompatible bitstream on an Intel® Agilex® device can result in one of the following:
  • Successful PR programming, but corrupted FPGA functionality
  • Unsuccessful PR programming, and corrupted FPGA functionality
If you wish to reprogram a child PR region on the FPGA, you must ensure that the child PR .rbf is generated from an implementation revision compile whose parent PR persona matches the persona currently on the FPGA. For example, when you program the base blinking_led.sof onto the FPGA, the parent PR persona is default. The child PR persona is default as well. To change the child PR persona to slow persona, you have the choice of using the following bitstreams:
  1. hpr_child_slow.pr_parent_partition.pr_partition.rbf
  2. hpr_parent_slow_child_slow.pr_parent_partition.pr_partition.rbf
In this case, you must choose the hpr_child_slow.pr_parent_partition.pr_partition.rbf bitstream, because the hpr_child_slow.pr_parent_partition.pr_partition.rbf is generated by an implementation revision that has the default parent persona. Choosing hpr_parent_slow_child_slow.pr_parent_partition.pr_partition.rbf results in unsuccessful PR programming, corrupted FPGA functionality, or both.
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