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Ixiasoft
Step 1: Getting Started
Step 2: Creating a Child Level Submodule
Step 3: Creating Design Partitions
Step 4: Allocating Placement and Routing Region for PR Partitions
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing the PR Implementation Revisions for Parent PR Partition
Step 9: Preparing the PR Implementation Revisions for Child PR Partitions
Step 10: Programming the Board
Modifying an Existing Persona
Adding a New Persona to the Design
Visible to Intel only — GUID: vvg1623773186771
Ixiasoft
Reference Design Walkthrough
The following steps describe the application of partial reconfiguration to a flat design. The tutorial uses the Intel® Quartus® Prime Pro Edition software for the Intel® Agilex® F-Series FPGA development board:
- Step 1: Getting Started
- Step 2: Creating a Child Level Submodule
- Step 3: Creating Design Partitions
- Step 4: Allocating Placement and Routing Region for PR Partitions
- Step 5: Defining Personas
- Step 6: Creating Revisions
- Step 7: Compiling the Base Revision
- Step 8: Preparing the PR Implementation Revisions for Parent PR Partition
- Step 9: Preparing the PR Implementation Revisions for Child PR Partitions
- Step 10: Programming the Board
- Step 1: Getting Started
- Step 2: Creating a Child Level Submodule
- Step 3: Creating Design Partitions
- Step 4: Allocating Placement and Routing Region for PR Partitions
- Step 5: Defining Personas
- Step 6: Creating Revisions
- Step 7: Compiling the Base Revision
- Step 8: Preparing the PR Implementation Revisions for Parent PR Partition
- Step 9: Preparing the PR Implementation Revisions for Child PR Partitions
- Step 10: Programming the Board
- Modifying an Existing Persona
- Adding a New Persona to the Design