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Ixiasoft
Step 1: Getting Started
Step 2: Creating a Child Level Submodule
Step 3: Creating Design Partitions
Step 4: Allocating Placement and Routing Region for PR Partitions
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing the PR Implementation Revisions for Parent PR Partition
Step 9: Preparing the PR Implementation Revisions for Child PR Partitions
Step 10: Programming the Board
Modifying an Existing Persona
Adding a New Persona to the Design
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Ixiasoft
Document Revision History for AN 954: Hierarchical Partial Reconfiguration Tutorial for Intel® Agilex® F-Series FPGA Development Board
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2021.08.04 | 21.1 | Initial release. |