Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

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ID 683641
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Design Optimization Overview 2. Optimizing the Design Netlist 3. Netlist Optimizations and Physical Synthesis 4. Area Optimization 5. Timing Closure and Optimization 6. Analyzing and Optimizing the Design Floorplan 7. Using the ECO Compilation Flow 8. Intel® Quartus® Prime Pro Edition Design Optimization User Guide Archives A. Intel® Quartus® Prime Pro Edition User Guides
1. Design Optimization Overview x
1.1. Device Considerations 1.2. Required Settings for Initial Compilation 1.3. Optimization Trade-Offs and Limitations 1.4. Design Visualization and Optimization Tools 1.5. Design Optimization Overview Revision History
1.1. Device Considerations x
1.1.1. Device Migration Considerations
1.2. Required Settings for Initial Compilation x
1.2.1. Initial I/O Assignment Guidelines 1.2.2. Initial Timing Constraint Guidelines
1.3. Optimization Trade-Offs and Limitations x
1.3.1. Area Reduction Trade-Offs 1.3.2. Critical Path Delay Reduction Trade-Offs 1.3.3. Power Consumption Reduction Trade-Offs 1.3.4. Compilation Time Trade-Offs
1.4. Design Visualization and Optimization Tools x
1.4.1. Design Visualization Tools 1.4.2. Design Optimization Tools
2. Optimizing the Design Netlist x
2.1. When to Use the Netlist Viewers: Analyzing Design Problems 2.2. Intel® Quartus® Prime Design Flow with the Netlist Viewers 2.3. RTL Viewer Overview 2.4. Technology Map Viewer Overview 2.5. Netlist Viewer User Interface 2.6. Schematic View 2.7. Cross-Probing to a Source Design File and Other Intel® Quartus® Prime Windows 2.8. Cross-Probing to the Netlist Viewers from Other Intel® Quartus® Prime Windows 2.9. Viewing a Timing Path 2.10. Optimizing the Design Netlist Revision History
2.3. RTL Viewer Overview x
2.3.1. Maximizing Readability in RTL Viewer 2.3.2. Running the RTL Viewer
2.5. Netlist Viewer User Interface x
2.5.1. Netlist Navigator Pane 2.5.2. Properties Pane 2.5.3. Netlist Viewers Find Pane
2.6. Schematic View x
2.6.1. Display Schematics in Multiple Tabbed View 2.6.2. Schematic Symbols 2.6.3. Select Items in the Schematic View 2.6.4. Shortcut Menu Commands in the Schematic View 2.6.5. Filtering in the Schematic View 2.6.6. View Contents of Nodes in the Schematic View 2.6.7. Moving Nodes in the Schematic View 2.6.8. View LUT Representations in the Technology Map Viewer 2.6.9. Zoom Controls 2.6.10. Navigating with the Bird's Eye View 2.6.11. Partition the Schematic into Pages 2.6.12. Follow Nets Across Schematic Pages
3. Netlist Optimizations and Physical Synthesis x
3.1. Physical Synthesis Optimizations 3.2. Applying Netlist Optimizations 3.3. Scripting Support 3.4. Netlist Optimizations and Physical Synthesis Revision History
3.1. Physical Synthesis Optimizations x
3.1.1. Enabling Physical Synthesis Optimization 3.1.2. Physical Synthesis Options
3.2. Applying Netlist Optimizations x
3.2.1. WYSIWYG Primitive Resynthesis
3.3. Scripting Support x
3.3.1. Synthesis Netlist Optimizations 3.3.2. Physical Synthesis Optimizations
4. Area Optimization x
4.1. Resource Utilization Information 4.2. Optimizing Resource Utilization 4.3. Scripting Support 4.4. Area Optimization Revision History
4.1. Resource Utilization Information x
4.1.1. Flow Summary Report 4.1.2. Fitter Reports 4.1.3. Analysis and Synthesis Reports 4.1.4. Compilation Messages
4.2. Optimizing Resource Utilization x
4.2.1. Resource Utilization Issues Overview 4.2.2. I/O Pin Utilization or Placement 4.2.3. Logic Utilization or Placement 4.2.4. Routing
4.2.2. I/O Pin Utilization or Placement x
4.2.2.1. Guideline: Modify Pin Assignments or Choose a Larger Package
4.2.3. Logic Utilization or Placement x
4.2.3.1. Guideline: Optimize Source Code 4.2.3.2. Guideline: Optimize Synthesis for Area, Not Speed 4.2.3.3. Guideline: Restructure Multiplexers 4.2.3.4. Guideline: Perform WYSIWYG Primitive Resynthesis with Balanced or Area Setting 4.2.3.5. Guideline: Use Register Packing 4.2.3.6. Guideline: Remove Fitter Constraints 4.2.3.7. Guideline: Flatten the Hierarchy During Synthesis 4.2.3.8. Guideline: Re-target Memory Blocks 4.2.3.9. Guideline: Use Physical Synthesis Options to Reduce Area 4.2.3.10. Guideline: Retarget or Balance DSP Blocks 4.2.3.11. Guideline: Use a Larger Device
4.2.4. Routing x
4.2.4.1. Guideline: Set Auto Packed Registers to Sparse or Sparse Auto 4.2.4.2. Guideline: Set Fitter Aggressive Routability Optimizations to Always 4.2.4.3. Guideline: Increase Router Effort Multiplier 4.2.4.4. Guideline: Remove Fitter Constraints 4.2.4.5. Guideline: Optimize Synthesis for Area, Not Speed 4.2.4.6. Guideline: Optimize Source Code 4.2.4.7. Guideline: Use a Larger Device
4.3. Scripting Support x
4.3.1. Initial Compilation Settings 4.3.2. Resource Utilization Optimization Techniques
5. Timing Closure and Optimization x
5.1. Optimize Multi Corner Timing 5.2. Optimize Critical Paths 5.3. Optimize Critical Chains 5.4. Design Evaluation for Timing Closure 5.5. Timing Optimization 5.6. Periphery to Core Register Placement and Routing Optimization 5.7. Scripting Support 5.8. Timing Closure and Optimization Revision History
5.2. Optimize Critical Paths x
5.2.1. Viewing Critical Paths
5.3. Optimize Critical Chains x
5.3.1. Viewing Critical Chains
5.4. Design Evaluation for Timing Closure x
5.4.1. Review Messages 5.4.2. Evaluate Fitter Netlist Optimizations 5.4.3. Evaluate Optimization Results 5.4.4. Evaluate Resource Usage 5.4.5. Evaluate Other Reports and Adjust Settings Accordingly 5.4.6. Evaluate Clustering Difficulty 5.4.7. Revise and Recompile
5.4.4. Evaluate Resource Usage x
5.4.4.1. Evaluate Global and Non-Global Usage 5.4.4.2. Evaluate Routing Usage 5.4.4.3. Evaluate Wires Added for Hold
5.5. Timing Optimization x
5.5.1. Correct Design Assistant Rule Violations 5.5.2. Implement Fast Forward Timing Closure Recommendations 5.5.3. View Timing Optimization Advisor 5.5.4. Review Timing Path Details 5.5.5. Try Optional Fitter Settings 5.5.6. Back-Annotate Optimized Assignments 5.5.7. Optimize Settings with Design Space Explorer II 5.5.8. I/O Timing Optimization Techniques 5.5.9. Register-to-Register Timing Optimization Techniques 5.5.10. Metastability Analysis and Optimization Techniques
5.5.2. Implement Fast Forward Timing Closure Recommendations x
5.5.2.1. Retiming Limit Details Report 5.5.2.2. Fast Forward Timing Closure Recommendations
5.5.2.1. Retiming Limit Details Report x
5.5.2.1.1. Using the Retiming Limit Details Report
5.5.2.2. Fast Forward Timing Closure Recommendations x
5.5.2.2.1. Generating Fast Forward Timing Closure Recommendations 5.5.2.2.2. Implementing Fast Forward Recommendations
5.5.4. Review Timing Path Details x
5.5.4.1. Report Timing 5.5.4.2. Report Logic Depth 5.5.4.3. Report Neighbor Paths 5.5.4.4. Report Register Spread 5.5.4.5. Report Route Net of Interest 5.5.4.6. Report Retiming Restrictions 5.5.4.7. Report Pipelining Information 5.5.4.8. Report CDC Viewer 5.5.4.9. Timing Closure Recommendations 5.5.4.10. Global Network Buffers 5.5.4.11. Resets and Global Networks 5.5.4.12. Suspicious Setup 5.5.4.13. Auto Shift Register Replacement 5.5.4.14. Clocking Architecture
5.5.4.10. Global Network Buffers x
5.5.4.10.1. Source Location 5.5.4.10.2. Insertion Delay 5.5.4.10.3. Fan-Out 5.5.4.10.4. Global Signal Assignment
5.5.5. Try Optional Fitter Settings x
5.5.5.1. Optimize Hold Timing 5.5.5.2. Fitter Aggressive Routability Optimization
5.5.7. Optimize Settings with Design Space Explorer II x
5.5.7.1. DSE II Computing Resources 5.5.7.2. DSE II Optimization Parameters 5.5.7.3. DSE II Result Management 5.5.7.4. Running DSE II
5.5.8. I/O Timing Optimization Techniques x
5.5.8.1. I/O Timing Constraints 5.5.8.2. Optimize IOC Register Placement for Timing Logic Option 5.5.8.3. Fast Input, Output, and Output Enable Registers 5.5.8.4. Programmable Delays 5.5.8.5. Use PLLs to Shift Clock Edges 5.5.8.6. Use Fast Regional Clock Networks and Regional Clocks Networks 5.5.8.7. Spine Clock Limitations
5.5.9. Register-to-Register Timing Optimization Techniques x
5.5.9.1. Optimize Source Code 5.5.9.2. Improving Register-to-Register Timing 5.5.9.3. Physical Synthesis Optimizations 5.5.9.4. Set Power Optimization During Synthesis to Normal Compilation 5.5.9.5. Optimize Synthesis for Speed, Not Area 5.5.9.6. Flatten the Hierarchy During Synthesis 5.5.9.7. Set the Synthesis Effort to High 5.5.9.8. Duplicate Registers for Fan-Out Control 5.5.9.9. Prevent Shift Register Inference 5.5.9.10. Use Other Synthesis Options Available in Your Synthesis Tool 5.5.9.11. Fitter Seed 5.5.9.12. Set Maximum Router Timing Optimization Level 5.5.9.13. Register-to-Register Timing Analysis
5.5.9.8. Duplicate Registers for Fan-Out Control x
5.5.9.8.1. Manual Register Duplication 5.5.9.8.2. Automatic Register Duplication: Estimated Physical Proximity 5.5.9.8.3. Automatic Register Duplication: Hierarchical Proximity
5.5.9.13. Register-to-Register Timing Analysis x
5.5.9.13.1. Tips for Analyzing Failing Paths 5.5.9.13.2. Tips for Analyzing Failing Clock Paths that Cross Clock Domains 5.5.9.13.3. Tips for Critical Path Analysis 5.5.9.13.4. Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles 5.5.9.13.5. Global Routing Resources
5.6. Periphery to Core Register Placement and Routing Optimization x
5.6.1. Setting Periphery to Core Optimizations in the Advanced Fitter Setting Dialog Box 5.6.2. Setting Periphery to Core Optimizations in the Assignment Editor 5.6.3. Viewing Periphery to Core Optimizations in the Fitter Report
5.7. Scripting Support x
5.7.1. Initial Compilation Settings 5.7.2. I/O Timing Optimization Techniques 5.7.3. Register-to-Register Timing Optimization Techniques
6. Analyzing and Optimizing the Design Floorplan x
6.1. Design Floorplan Analysis in the Chip Planner 6.2. Creating Partitions and Logic Lock Regions with the Design Partition Planner and the Chip Planner 6.3. Using Logic Lock Regions in the Chip Planner 6.4. Using User-Defined Clock Regions in the Chip Planner 6.5. Scripting Support 6.6. Analyzing and Optimizing the Design Floorplan Revision History
6.1. Design Floorplan Analysis in the Chip Planner x
6.1.1. Starting the Chip Planner 6.1.2. Chip Planner GUI Components 6.1.3. Viewing Design Elements in the Chip Planner 6.1.4. Exploring Paths in the Chip Planner 6.1.5. Viewing Assignments in the Chip Planner 6.1.6. Viewing High-Speed and Low-Power Tiles in the Chip Planner
6.1.2. Chip Planner GUI Components x
6.1.2.1. Chip Planner Toolbar 6.1.2.2. Layers Settings 6.1.2.3. Locate History Window 6.1.2.4. Chip Planner Floorplan Views
6.1.3. Viewing Design Elements in the Chip Planner x
6.1.3.1. Viewing Architecture-Specific Design Information 6.1.3.2. Viewing Available Clock Networks in the Device 6.1.3.3. Viewing Clock Sector Utilization 6.1.3.4. Viewing Routing Congestion 6.1.3.5. Viewing I/O Banks 6.1.3.6. Viewing High-Speed Serial Interfaces (HSSI) 6.1.3.7. Viewing the Source and Destination of Placed Nodes 6.1.3.8. Viewing Fan-In and Fan-Out Connections of Placed Resources 6.1.3.9. Viewing Immediate Fan-In and Fan-Out Connections 6.1.3.10. Viewing Selected Contents
6.1.4. Exploring Paths in the Chip Planner x
6.1.4.1. Analyzing Connections for a Path 6.1.4.2. Locate Path from the Timing Analysis Report to the Chip Planner 6.1.4.3. Show Delays 6.1.4.4. Viewing Routing Resources
6.2. Creating Partitions and Logic Lock Regions with the Design Partition Planner and the Chip Planner x
6.2.1. Viewing Design Connectivity and Hierarchy
6.3. Using Logic Lock Regions in the Chip Planner x
6.3.1. Viewing Connections Between Logic Lock Regions in the Chip Planner 6.3.2. Logic Lock Regions 6.3.3. Attributes of a Logic Lock Region 6.3.4. Migrating Assignments between Intel® Quartus® Prime Standard Edition and Intel® Quartus® Prime Pro Edition 6.3.5. Creating Logic Lock Regions 6.3.6. Customizing the Shape of Logic Lock Regions 6.3.7. Placing Device Resources into Logic Lock Regions 6.3.8. Hierarchical Regions 6.3.9. Additional Intel® Quartus® Prime Logic Lock Design Features 6.3.10. Logic Lock Regions Window 6.3.11. Snapping to a Region
6.3.5. Creating Logic Lock Regions x
6.3.5.1. Creating Logic Lock Regions with the Chip Planner 6.3.5.2. Creating Logic Lock Regions with the Project Navigator 6.3.5.3. Creating Logic Lock Regions with the Logic Lock Regions Window 6.3.5.4. Defining Routing Regions 6.3.5.5. Noncontiguous Logic Lock Regions 6.3.5.6. Considerations on Using Auto Sized Regions
6.3.6. Customizing the Shape of Logic Lock Regions x
6.3.6.1. Adding a New Shape to a Logic Lock Region 6.3.6.2. Subtracting Shape from Logic Lock Region 6.3.6.3. Merging Logic Lock Regions 6.3.6.4. Noncontiguous Logic Lock Regions
6.3.7. Placing Device Resources into Logic Lock Regions x
6.3.7.1. Empty Logic Lock Regions 6.3.7.2. Pin Assignment 6.3.7.3. Reserved Logic Lock Regions 6.3.7.4. Virtual Pins 6.3.7.5. Example: Placement Best Practices for Intel® Arria® 10 FPGAs
6.3.9. Additional Intel® Quartus® Prime Logic Lock Design Features x
6.3.9.1. Intel® Quartus® Prime Revisions Feature
6.4. Using User-Defined Clock Regions in the Chip Planner x
6.4.1. Creating Clock Assignments with the Chip Planner 6.4.2. Resizing a Clock Assignment 6.4.3. Moving a Clock Assignment 6.4.4. Deleting a Clock Region Assignment 6.4.5. Assigning a Clock Signal to a Clock Region 6.4.6. Clock Assignment Properties
6.5. Scripting Support x
6.5.1. Creating Logic Lock Assignments with Tcl commands 6.5.2. Assigning Virtual Pins with a Tcl command 6.5.3. Logic Lock Region Assignment Examples
7. Using the ECO Compilation Flow x
7.1. ECO Compilation Flow 7.2. ECO Tcl Script Example 7.3. Viewing ECO Compilation Reports 7.4. ECO Commands 7.5. ECO Command Limitations 7.6. Interactive ECO Fitting 7.7. Using the ECO Compilation Flow Revision History
7.4. ECO Commands x
7.4.1. ECO Command Quick Reference 7.4.2. make_connection 7.4.3. remove_connection 7.4.4. modify_lutmask 7.4.5. adjust_pll_refclk 7.4.6. modify_io_slew_rate 7.4.7. modify_io_current_strength 7.4.8. modify_io_delay_chain 7.4.9. create_new_node 7.4.10. remove_node 7.4.11. place_node 7.4.12. unplace_node 7.4.13. create_wirelut
7.6. Interactive ECO Fitting x
7.6.1. eco_load_design and eco_commit_design Commands
1. Design Optimization Overview
2. Optimizing the Design Netlist
3. Netlist Optimizations and Physical Synthesis
4. Area Optimization
5. Timing Closure and Optimization
6. Analyzing and Optimizing the Design Floorplan
7. Using the ECO Compilation Flow
8. Intel® Quartus® Prime Pro Edition Design Optimization User Guide Archives
A. Intel® Quartus® Prime Pro Edition User Guides

6.1.3.4. Viewing Routing Congestion

The Report Routing Utilization task allows you to determine the percentage of routing resources in use following a compilation. This feature can identify zones with lack of routing resources, helping you to make design changes to meet routing congestion design requirements.

To view the routing congestion in the Chip Planner:

  1. In the Tasks pane, double-click the Report Routing Utilization command to launch the Report Routing Utilization dialog box.
  2. Click Preview in the Report Routing Utilization dialog box to preview the default congestion display.
  3. Change the Routing Utilization Type to display congestion for specific resources.
    The default display uses dark blue for 0% congestion (blue indicates zero utilization) and red for 100%. You can adjust the slider for Threshold percentage to change the congestion threshold level.

The congestion map helps you determine whether you can modify the floorplan, or modify the RTL to reduce routing congestion. Consider:

  • The routing congestion map uses the color and shading of logic resources to indicate relative resource utilization; darker shading represents a greater utilization of routing resources. Areas where routing utilization exceeds the threshold value that you specify in the Report Routing Utilization dialog box appear in red.
  • To identify a lack of routing resources, you must investigate each routing interconnect type separately by selecting each interconnect type in turn in the Routing Utilization Settings dialog box.
  • The Compiler's messages contain information about average and peak interconnect usage. Peak interconnect usage over 75%, or average interconnect usage over 60%, can indicate difficulties fitting your design. Similarly, peak interconnect usage over 90%, or average interconnect usage over 75%, show increased chances of not getting a valid fit.
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