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1. Design Optimization Overview
2. Optimizing the Design Netlist
3. Netlist Optimizations and Physical Synthesis
4. Area Optimization
5. Timing Closure and Optimization
6. Analyzing and Optimizing the Design Floorplan
7. Using the ECO Compilation Flow
8. Intel® Quartus® Prime Pro Edition Design Optimization User Guide Archives
A. Intel® Quartus® Prime Pro Edition User Guides
2.1. When to Use the Netlist Viewers: Analyzing Design Problems
2.2. Intel® Quartus® Prime Design Flow with the Netlist Viewers
2.3. RTL Viewer Overview
2.4. Technology Map Viewer Overview
2.5. Netlist Viewer User Interface
2.6. Schematic View
2.7. Cross-Probing to a Source Design File and Other Intel® Quartus® Prime Windows
2.8. Cross-Probing to the Netlist Viewers from Other Intel® Quartus® Prime Windows
2.9. Viewing a Timing Path
2.10. Optimizing the Design Netlist Revision History
2.6.1. Display Schematics in Multiple Tabbed View
2.6.2. Schematic Symbols
2.6.3. Select Items in the Schematic View
2.6.4. Shortcut Menu Commands in the Schematic View
2.6.5. Filtering in the Schematic View
2.6.6. View Contents of Nodes in the Schematic View
2.6.7. Moving Nodes in the Schematic View
2.6.8. View LUT Representations in the Technology Map Viewer
2.6.9. Zoom Controls
2.6.10. Navigating with the Bird's Eye View
2.6.11. Partition the Schematic into Pages
2.6.12. Follow Nets Across Schematic Pages
4.2.3.1. Guideline: Optimize Source Code
4.2.3.2. Guideline: Optimize Synthesis for Area, Not Speed
4.2.3.3. Guideline: Restructure Multiplexers
4.2.3.4. Guideline: Perform WYSIWYG Primitive Resynthesis with Balanced or Area Setting
4.2.3.5. Guideline: Use Register Packing
4.2.3.6. Guideline: Remove Fitter Constraints
4.2.3.7. Guideline: Flatten the Hierarchy During Synthesis
4.2.3.8. Guideline: Re-target Memory Blocks
4.2.3.9. Guideline: Use Physical Synthesis Options to Reduce Area
4.2.3.10. Guideline: Retarget or Balance DSP Blocks
4.2.3.11. Guideline: Use a Larger Device
4.2.4.1. Guideline: Set Auto Packed Registers to Sparse or Sparse Auto
4.2.4.2. Guideline: Set Fitter Aggressive Routability Optimizations to Always
4.2.4.3. Guideline: Increase Router Effort Multiplier
4.2.4.4. Guideline: Remove Fitter Constraints
4.2.4.5. Guideline: Optimize Synthesis for Area, Not Speed
4.2.4.6. Guideline: Optimize Source Code
4.2.4.7. Guideline: Use a Larger Device
5.1. Optimize Multi Corner Timing
5.2. Optimize Critical Paths
5.3. Optimize Critical Chains
5.4. Design Evaluation for Timing Closure
5.5. Timing Optimization
5.6. Periphery to Core Register Placement and Routing Optimization
5.7. Scripting Support
5.8. Timing Closure and Optimization Revision History
5.5.1. Correct Design Assistant Rule Violations
5.5.2. Implement Fast Forward Timing Closure Recommendations
5.5.3. View Timing Optimization Advisor
5.5.4. Review Timing Path Details
5.5.5. Try Optional Fitter Settings
5.5.6. Back-Annotate Optimized Assignments
5.5.7. Optimize Settings with Design Space Explorer II
5.5.8. I/O Timing Optimization Techniques
Summary of Techniques for Improving Setup and Clock-to-Output Times
5.5.9. Register-to-Register Timing Optimization Techniques
5.5.10. Metastability Analysis and Optimization Techniques
5.5.4.1. Report Timing
5.5.4.2. Report Logic Depth
5.5.4.3. Report Neighbor Paths
5.5.4.4. Report Register Spread
5.5.4.5. Report Route Net of Interest
5.5.4.6. Report Retiming Restrictions
5.5.4.7. Report Pipelining Information
5.5.4.8. Report CDC Viewer
5.5.4.9. Timing Closure Recommendations
5.5.4.10. Global Network Buffers
5.5.4.11. Resets and Global Networks
5.5.4.12. Suspicious Setup
5.5.4.13. Auto Shift Register Replacement
5.5.4.14. Clocking Architecture
Summary of Techniques for Improving Setup and Clock-to-Output Times
5.5.8.1. I/O Timing Constraints
5.5.8.2. Optimize IOC Register Placement for Timing Logic Option
5.5.8.3. Fast Input, Output, and Output Enable Registers
5.5.8.4. Programmable Delays
5.5.8.5. Use PLLs to Shift Clock Edges
5.5.8.6. Use Fast Regional Clock Networks and Regional Clocks Networks
5.5.8.7. Spine Clock Limitations
5.5.9.1. Optimize Source Code
5.5.9.2. Improving Register-to-Register Timing
5.5.9.3. Physical Synthesis Optimizations
5.5.9.4. Set Power Optimization During Synthesis to Normal Compilation
5.5.9.5. Optimize Synthesis for Speed, Not Area
5.5.9.6. Flatten the Hierarchy During Synthesis
5.5.9.7. Set the Synthesis Effort to High
5.5.9.8. Duplicate Registers for Fan-Out Control
5.5.9.9. Prevent Shift Register Inference
5.5.9.10. Use Other Synthesis Options Available in Your Synthesis Tool
5.5.9.11. Fitter Seed
5.5.9.12. Set Maximum Router Timing Optimization Level
5.5.9.13. Register-to-Register Timing Analysis
6.1. Design Floorplan Analysis in the Chip Planner
6.2. Creating Partitions and Logic Lock Regions with the Design Partition Planner and the Chip Planner
6.3. Using Logic Lock Regions in the Chip Planner
6.4. Using User-Defined Clock Regions in the Chip Planner
6.5. Scripting Support
6.6. Analyzing and Optimizing the Design Floorplan Revision History
6.1.3.1. Viewing Architecture-Specific Design Information
6.1.3.2. Viewing Available Clock Networks in the Device
6.1.3.3. Viewing Clock Sector Utilization
6.1.3.4. Viewing Routing Congestion
6.1.3.5. Viewing I/O Banks
6.1.3.6. Viewing High-Speed Serial Interfaces (HSSI)
6.1.3.7. Viewing the Source and Destination of Placed Nodes
6.1.3.8. Viewing Fan-In and Fan-Out Connections of Placed Resources
6.1.3.9. Viewing Immediate Fan-In and Fan-Out Connections
6.1.3.10. Viewing Selected Contents
6.3.1. Viewing Connections Between Logic Lock Regions in the Chip Planner
6.3.2. Logic Lock Regions
6.3.3. Attributes of a Logic Lock Region
6.3.4. Migrating Assignments between Intel® Quartus® Prime Standard Edition and Intel® Quartus® Prime Pro Edition
6.3.5. Creating Logic Lock Regions
6.3.6. Customizing the Shape of Logic Lock Regions
6.3.7. Placing Device Resources into Logic Lock Regions
6.3.8. Hierarchical Regions
6.3.9. Additional Intel® Quartus® Prime Logic Lock Design Features
6.3.10. Logic Lock Regions Window
6.3.11. Snapping to a Region
6.3.5.1. Creating Logic Lock Regions with the Chip Planner
6.3.5.2. Creating Logic Lock Regions with the Project Navigator
6.3.5.3. Creating Logic Lock Regions with the Logic Lock Regions Window
6.3.5.4. Defining Routing Regions
6.3.5.5. Noncontiguous Logic Lock Regions
6.3.5.6. Considerations on Using Auto Sized Regions
7.4.1. ECO Command Quick Reference
7.4.2. make_connection
7.4.3. remove_connection
7.4.4. modify_lutmask
7.4.5. adjust_pll_refclk
7.4.6. modify_io_slew_rate
7.4.7. modify_io_current_strength
7.4.8. modify_io_delay_chain
7.4.9. create_new_node
7.4.10. remove_node
7.4.11. place_node
7.4.12. unplace_node
7.4.13. create_wirelut
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5.5.8. I/O Timing Optimization Techniques
This stage of design optimization focuses on I/O timing, including setup delay (tSU), hold time (tH), and clock-to-output (tCO) parameters.
Before proceeding with I/O timing optimization, ensure that:
- The design's assignments follow the suggestions in the Initial Compilation: Required Settings section of the Design Optimization Overview chapter.
- Resource utilization is satisfactory.
Note: Complete this stage before proceeding to the register-to-register timing optimization stage. Changes to the I/O paths affect the internal register-to-register timing.
Summary of Techniques for Improving Setup and Clock-to-Output Times
The table lists the recommended order of techniques to reduce tSU and tCO times. Reducing tSU times increases hold (tH) times.
Note: Verify which options are available to each device family
Order | Technique | Affects tSU | Affects tCO |
---|---|---|---|
1 | Verify of that the appropriate constraints are set for the failing I/Os (refer to Initial Compilation: Required Settings) | Yes | Yes |
2 | Use timing-driven compilation for I/O (refer to Fast Input, Output, and Output Enable Registers) | Yes | Yes |
3 | Use fast input register (refer to Programmable Delays) | Yes | N/A |
4 | Use fast output register, fast output enable register, and fast OCT register (refer to Programmable Delays) | N/A | Yes |
5 | Decrease the value of Input Delay from Pin to Input Register or set Decrease Input Delay to Input Register = ON | Yes | N/A |
6 | Decrease the value of Input Delay from Pin to Internal Cells or set Decrease Input Delay to Internal Cells = ON | Yes | N/A |
7 | Decrease the value of Delay from Output Register to Output Pin or set Increase Delay to Output Pin = OFF (refer to Fast Input, Output, and Output Enable Registers) | N/A | Yes |
8 | Increase the value of Input Delay from Dual-Purpose Clock Pin to Fan-Out Destinations (refer to Fast Input, Output, and Output Enable Registers) | Yes | N/A |
9 | Use PLLs to shift clock edges | Yes | Yes |
10 | Increase the value of Delay to output enable pin or set Increase delay to output enable pin (refer to Use PLLs to Shift Clock Edges) | N/A | Yes |