Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

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ID 683628
Date 12/28/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core 2. Getting Started 3. Functional Description 4. Debugging the Link A. Arria 10 10GBASE-KR Registers B. Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.1 C. Additional Information
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core x
1.1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features 1.2. Low Latency 40-100GbE IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. Low Latency 40-100GbE IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. Low Latency 40-100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Stratix V Resource Utilization for Low Latency 40-100GbE IP Cores 1.4.2. Arria 10 Resource Utilization for Low Latency 40-100GbE IP Cores
2. Getting Started x
2.1. Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices 2.2. Licensing IP Cores 2.3. Specifying the Low Latency 40-100GbE IP Core Parameters and Options 2.4. IP Core Parameters 2.5. Files Generated for Stratix V Variations 2.6. Files Generated for Arria 10 Variations 2.7. Integrating Your IP Core in Your Design 2.8. Low Latency 40-100GbE IP Core Testbenches 2.9. Simulating the Low Latency 40‑100GbE IP Core With the Testbenches 2.10. Compiling the Full Design and Programming the FPGA 2.11. Initializing the IP Core
2.2. Licensing IP Cores x
2.2.1. OpenCore Plus IP Evaluation
2.7. Integrating Your IP Core in Your Design x
2.7.1. Pin Assignments 2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.7.3. Transceiver PLL Required in Arria 10 Designs 2.7.4. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.5. Clock Requirements for 40GBASE-KR4 Variations 2.7.6. External TX MAC PLL 2.7.7. Placement Settings for the Low Latency 40-100GbE IP Core
2.8. Low Latency 40-100GbE IP Core Testbenches x
2.8.1. Low Latency 40-100GbE IP Core Testbench Overview 2.8.2. Understanding the Testbench Behavior
2.9. Simulating the Low Latency 40‑100GbE IP Core With the Testbenches x
2.9.1. Generating the Low Latency 40-100GbE Testbench 2.9.2. Optimizing the Low Latency 40‑100GbE IP Core Simulation With the Testbenches 2.9.3. Simulating with the Modelsim Simulator 2.9.4. Simulating with the NCSim Simulator 2.9.5. Simulating with the VCS Simulator 2.9.6. Testbench Output Example: Low Latency 40-100GbE IP Core
3. Functional Description x
3.1. High Level System Overview 3.2. Low Latency 40-100GbE MAC and PHY Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. Low Latency 40-100GbE MAC and PHY Functional Description x
3.2.1. Low Latency 40-100GbE IP Core TX Datapath 3.2.2. Low Latency 40-100GbE IP Core TX Data Bus Interfaces 3.2.3. Low Latency 40-100GbE IP Core RX Datapath 3.2.4. Low Latency 40-100GbE IP Core RX Data Bus Interface 3.2.5. Low Latency 100GbE CAUI–4 PHY 3.2.6. External Reconfiguration Controller 3.2.7. External Transceiver PLL 3.2.8. External TX MAC PLL 3.2.9. Congestion and Flow Control Using Pause Frames 3.2.10. Pause Control and Generation Interface 3.2.11. Pause Control Frame Filtering 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. 1588 Precision Time Protocol Interfaces 3.2.15. PHY Status Interface 3.2.16. Transceiver PHY Serial Data Interface 3.2.17. Low Latency 40GBASE-KR4 IP Core Variations 3.2.18. Control and Status Interface 3.2.19. Arria 10 Transceiver Reconfiguration Interface 3.2.20. Clocks 3.2.21. Resets
3.2.1. Low Latency 40-100GbE IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter‑Packet Gap Generation and Insertion 3.2.1.7. Error Insertion Test and Debug Feature
3.2.2. Low Latency 40-100GbE IP Core TX Data Bus Interfaces x
3.2.2.1. Low Latency 40-100GbE IP Core User Interface Data Bus 3.2.2.2. Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. Low Latency 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. Order of Transmission
3.2.3. Low Latency 40-100GbE IP Core RX Datapath x
3.2.3.1. Low Latency 40-100GbE IP Core RX Filtering 3.2.3.2. 40-100GbE IP Core Preamble Processing 3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. 40-100GbE IP Core CRC Checking 3.2.3.5. LL 40-100GbE IP Core Malformed Packet Handling 3.2.3.6. RX CRC Forwarding 3.2.3.7. Inter-Packet Gap 3.2.3.8. Pause Ignore 3.2.3.9. Control Frame Identification
3.2.4. Low Latency 40-100GbE IP Core RX Data Bus Interface x
3.2.4.1. Low Latency 40-100GbE IP Core User Interface Data Bus 3.2.4.2. Low Latency 40-100GbE IP Core RX Data Bus 3.2.4.3. Low Latency 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.9. Congestion and Flow Control Using Pause Frames x
3.2.9.1. Conditions Triggering XOFF Frame Transmission 3.2.9.2. Conditions Triggering XON Frame Transmission
3.2.13. Statistics Counters Interface x
3.2.13.1. OctetOK Count Interface
3.2.14. 1588 Precision Time Protocol Interfaces x
3.2.14.1. Implementing a 1588 System That Includes a LL 40-100GbE IP Core 3.2.14.2. PTP Receive Functionality 3.2.14.3. PTP Transmit Functionality 3.2.14.4. External Time-of-Day Module for 1588 PTP Variations 3.2.14.5. PTP Timestamp and TOD Formats 3.2.14.6. 1588 PTP Interface Signals
3.3. Signals x
3.3.1. Low Latency 40-100GbE IP Core Signals
3.4. Software Interface: Registers x
3.4.1. Low Latency 40-100GbE IP Core Registers 3.4.2. LL 40‑100GbE Hardware Design Example Registers
3.4.1. Low Latency 40-100GbE IP Core Registers x
3.4.1.1. PHY Registers 3.4.1.2. Link Fault Signaling Registers 3.4.1.3. LL 40GBASE-KR4 Registers 3.4.1.4. Low Latency 40-100GbE IP Core MAC Configuration Registers 3.4.1.5. Pause Registers 3.4.1.6. TX Statistics Registers 3.4.1.7. RX Statistics Registers 3.4.1.8. 1588 PTP Registers
3.4.2. LL 40‑100GbE Hardware Design Example Registers x
3.4.2.1. Packet Client Registers
4. Debugging the Link x
4.1. Creating a SignalTap II Debug File to Match Your Design Hierarchy
A. Arria 10 10GBASE-KR Registers x
A.1. 10GBASE-KR PHY Register Definitions
C. Additional Information x
C.1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Archives C.2. Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History C.3. How to Contact Altera C.4. Typographic Conventions
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core
2. Getting Started
3. Functional Description
4. Debugging the Link
A. Arria 10 10GBASE-KR Registers
B. Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.1
C. Additional Information

C.2. Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History

Table 52.  Document Revision History

Date

Compatible ACDS Version

Changes

2017.12.28 16.0 Added note to clarify that this user guide documents the 16.0 version of the IP core, and that as of 2017.12.28, the 16.0 version of the Stratix® V LL 40-100GbE IP core is the most recent Stratix® V LL 40-100GbE IP core available in the Self-Service Licensing Center. The current versions of the Arria® 10 40GbE and 100GbE IP cores are documented separately in the Low Latency 40-Gbps Ethernet IP Core User Guide and the Low Latency 100-Gbps Ethernet IP Core User Guide, respectively.
2016.05.02 16.0
2015.11.12 15.1
2015.11.02 15.1
  • Updated for new Quartus Prime software v15.1 release.
  • Added new Quick Start Guide chapter to accelerate familiarity with the IP core and document the new hardware design example and supporting parameter editor tab.
  • Added new parameters Enable Altera Debug Master Endpoint and Enable ODI acceleration logic to turn on these features in the Arria 10 Native PHY IP core that specifies the transceiver settings in Arria 10 variations of the LL 40-100GbE IP core. Refer to IP Core Parameters.
  • Updated descriptions of PTP support functionality to incorporate changes to the IP core v15.1.
    • Added support for fingerprint passing.
    • Added 64-bit timestamp interface option to TOD module and LL 40-100GbE IP core.
    • Added new parameters Enable 96b Time of Day Format, Enable 64b Time of Day Format, and Timestamp fingerprint width. Refer to IP Core Parameters.
    • Removed TX_PTP_STATUS register. To specify that the 1588 PTP module should always provide the timestamps in outbound Ethernet frames in V2 format or in V1 format, turn on only one of the new parameters Enable 96b Time of Day Format and Enable 64b Time of Day Format. If you turn on both of these parameters, you can specify the current timestamp format in one-step mode with the relevant format signal. In two-step mode, you can maintain both formats at once. To specify whether the IP core uses the one-step process or the two-step process, assert the appropriate signals for the desired process for the current packet. Refer to PTP Transmit Functionality, PTP Timestamp and TOD Formats, 1588 PTP Registers, IP Core Parameters, and 1588 PTP Interface Signals.
    • Added new 1588 PTP registers TX_PTP_ASYM_DELAY, TX_PTP_PMA_LATENCY, and RX_PTP_PMA_LATENCY. Refer to 1588 PTP Registers.
    • Added new signals and renamed all old top-level 1588 PTP block signals. Refer to 1588 PTP Interface Signals.
  • Corrected information about link fault signaling signals and registers, in Link Fault Signaling Interface and Link Fault Signaling Registers.
  • Clarified that you must assert the reset_async signal for a full ten clk_status cycles to ensure correct reset of the IP core. Refer to Resets.
  • Clarified that if you do not turn on Enable alignment EOP on FCS word, the delay from EOP to FCS error indication is non-deterministic. Refer to IP Core Parameters
  • Updated 40GBASE-KR4 registers. Refer to LL 40GBASE-KR4 Registers.
    • Added default value for 0xB0[12]: LT Failure Reset
    • Added two fields that were new in the 15.0 Update 1 release: 0xD0[18]: VOD Training Enable and 0xD0[19]: Bypass DFE
    • Added default value for 0xD0[21:20]: rx_ctle_mode
  • Added information about IP core behavior in case of loss of signal. Refer to Debugging the 40GbE and 100GbE Link.
  • Fixed description of PHY_FRAME_ERROR register at offset 0x323 to clarify it is not sticky. Refer to PHY Registers.
  • Added figure to help distinguish the TX transceiver PLL from the TX MAC PLL, in Transceiver PLL Required in Arria 10 Designs.
  • Corrected allowed frequency range for clk_status in description of Status clock rate parameter allowed values, in IP Core Parameters. The allowed frequency range remains correct at 100–125 MHz in other locations in the user guide.
  • Added missing reset values for various register fields.
  • Fixed assorted typos and formatting issues, including register field width in IPG_COL_REM register at offset 0x406.
2015.05.04 15.0
  • User guide part number change from UG-01150 to UG-01172.
  • Updated release-specific information for the software release v15.0.
  • Added Synchronous Ethernet support for Arria 10 variations. Documented new Enable SyncE parameter and new clk_rx_recover output signal. Described expected usage in Clocks.
  • Updated handling of received malformed packets, in LL 40-100GbE IP Core Malformed Packet Handling, to incorporate these changes in the IP core v15.0:
    • The IP core asserts the l<n>_rx_error[0] or rx_error[0] signal in the case of an unexpected control character that is not an Error character.
    • Both the LL 40GbE IP core and the LL 100GbE IP core handle received malformed packets the same way.
  • Updated the descriptions of l<n>_rx_error[0] and rx_error[0] from PHY error to malformed packet error.
  • Added new three-bit l<n>_rx_status and rx_status signals on the RX client interface. These signals explain the control frames that the IP core passes to the client interface. Refer to Low Latency 40-100GbE IP Core RX Data Bus and Low Latency 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface), and to new section Control Frame Identification.
  • Added new TX error insertion feature. User logic can direct the IP core to insert an error in an outgoing Ethernet frame, using the new l<n>_tx_error and tx_error input signals on the TX client interface. Refer to Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) and Low Latency 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface), and to new section Error Insertion Test and Debug Feature.
  • Updated description of priority-based flow control. Priority-based flow control is now available for both LL 40GbE IP core variations and LL 100GbE IP core variations. Previously it was available only in LL 100GbE variations.
  • Added new signal tx_lanes_stable, in PHY Status Interface.
  • Updated description of the rx_ctle_mode 40GBASE-KR4 register and added default value for Enable Arria 10 Calibration 40GBASE-KR4 register. Also corrected the bit range of the LP Coefficients Update register field. For these changes and other 40GBASE-KR4 register information specific to this IP core, refer to LL 40GBASE-KR4 Registers. For changes to the underlying Arria 10 10GBASE-KR PHY registers, refer to the Arria 10 Transceiver PHY User Guide or to the Arria 10 10GBASE-KR Registers appendix.
  • Corrected the addresses of the CNTR_TX_STATUS and CNTR_RX_STATUS registers.
  • Corrected the descriptions of the PHY_PCS_INDIRECT_ADDR and PHY_PCS_INDIRECT_DATA registers at offsets 0x314 and 0x315.
  • Added note recommending that designs with multiple LL 40-100GbE IP cores not use the ATX PLL HDL code that is currently provided with the IP core. This code is deprecated. Refer to Transceiver PLL Required in Arria 10 Designs.
  • Added clock information for multiple IP core top-level signals.
  • Added information about how to check for word lock and alignment marker lock, in Debugging the 40GbE and 100GbE Link.
  • Updated Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v14.1 appendix with information about the v15.0 IP core.
  • Clarified the different paths to the example design and testbench directories and scripts in variations that target different device families.
  • Added description of the AM_CNT_BITS parameter in Optimizing the Low Latency 40‑100GbE IP Core Simulation With the Testbenches. You might need to modify this parameter in your own simulation environment.
  • Removed text of optimization parameter display initial block from Optimizing the Low Latency 40‑100GbE IP Core Simulation With the Testbenches. Refer to the testbench for your IP core variation for the correct HDL code for the variation.
  • Changed default value of 40GBASE-KR4 link training PMA parameter INITPOSTVAL from 22 to 13, in IP Core Parameters.
  • Updated descriptions of IP core example project. The IP core now generates an example project that is configurable on a device, for most variations. The older type of example projects, which are not configurable, are also generated. Refer to Low Latency 40-100GbE IP Core Design Example.
  • Fixed assorted minor errors and typos.
2014.12.17 14.1
  • Corrected PTP usage figures in Implementing a 1588 System That Includes a LL 40-100GbE IP Core.
  • Clarified that user-defined extra latency is included in calculation of PTP exit timestamp in both one-step mode and two-step mode, in PTP Transmit Functionality.
  • Clarified that TOD module is expected to provide the current continuously updating time of day. The output signals of this module must provide the current time of day on every clock cycle, in V2 format.
  • Moved External Time-of-Day Module for 1588 PTP Variations into the 1588 PTP section of the Functional Description chapter.
2014.12.15 14.1
  • Updated release-specific information for the software release v14.1.
  • Moved licensing information and the description of the OpenCore Plus evaluation feature to Getting Started chapter.
  • Added option to instantiate the TX MAC PLL outside the IP core. The new PLL generates the TX MAC clock. Added new parameter Use external TX MAC PLL. If you turn on this parameter the IP core has an additional input clock signal clk_txmac_in.Changes primarily located in new sections External TX MAC PLL in Getting Started chapter and External TX MAC PLL in Functional Description chapter, in IP Core Parameters section, and in Clocks section.
  • Added support for new 40GBASE-KR4 LL 40GbE IP core variation. Changes located in existing IP Core Parameters section and descriptions of the testbench for these IP core variations in the Low Latency 40-100GbE IP Core Testbenches section. Added new sections Clock Requirements for 40GBASE-KR4 Variations, Low Latency 40GBASE-KR4 IP Core Variations, and LL 40GBASE-KR4 Registers, and a reference appendix Arria 10 10GBASE-KR Registers.
  • Added new six-bit RX error signal on client interface. On Avalon-ST client interface, l<n>_rx_error[5:0] replaces single-bit RX error signal l<n>_rx_error. On custom client interface, rx_error[5:0] is new signal.
  • Added information about how the IP core handles malformed packets it receives. Previously the IP core did not terminate an incoming packet if it receives an unexpected control character. Changes are located in the new LL 40-100GbE IP Core Malformed Packet Handling section.
  • Added two new 64-bit statistics counters RXOctets_OK (offset 0x960) and TxOctetsOK (offset 0x860) to count the payload bytes (octets) in received and transmitted frames with no FCS errors, undersized, oversized, or payload length errors.
  • Added four new signals in new octetsOK interface. These signals provide per-frame information about the octet count in the two new statistics counters: rx_inc_octetsOK, rx_inc_octetsOK_valid, tx_inc_octetsOK, tx_inc_octetsOK_valid. Refer to new section OctetOK Count Interface.
  • Added new CFG_PLEN_CHECK register at offset 0x50A, to support bit[4] of the new six-bit RX error signal.
  • Added new link fault signals unidirectional_en and link_fault_gen_en that provide status from the LINK_FAULT_CONFIG register.
  • Described new method for handling module-specific signals when the module is not included in your IP core variation. TX MAC input clock, link fault signals, pause signals, and PTP signals are not available in newly generated IP cores that do not include the relevant module. However, for backward compatibility, if you upgrade an IP core variation, link fault signals, pause signals, and PTP signals in the earlier release of the IP core variation remain available in the 14.1 version after upgrade.
  • Updated PTP module description and signals for current IP core version to support changes to the IP core 1588 PTP functionality. Corrected description of the tx_in_ptp_overwrite[1:0] signal. Improved usage description. If you turn on Enable 1588 PTP , the PTP module has the following new features and requirements::
    • You must instantiate a time-of-day module and connect it to the IP core. Previously, this module was included in the IP core. The change facilitates TOD module sharing among IP cores.
    • Added new PTP signals tod_rxmac_in and tod_txmac_in to receive the timestamps the TOD module generates in the two clock domains.
    • Removed TX PTP module TOD calculation registers at 0xB06 through 0xB08. The TOD module now provides the functionality the registers supported in previous versions of the IP core.
    • Added support for resetting the TCP checksum to zero if the application does not recalculate it. The new feature adds two new PTP signals tx_in_zero_tcp and tx_in_tcp_offset with which the application communicates such a request to the IP core.
  • Clarified that IP core does not identify frames of eight bytes or less as runts but instead as FCS errors.
  • Clarified that IP core does not generate frames of eight bytes or less.
  • Added waveform to illustrate register access on the control and status interface, in the Control and Status Interface section
  • Updated Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v14.1 appendix with information about the v14.1 IP core.
  • Corrected misinformation about the IP core variations that support the Enable TX CRC insertion parameter. Only IP core variations that do not support flow control provide this parameter.
  • Corrected order of TX_PFC_DADDRH (offset 0x60E) and TX_PFC_DADDRL (offset 0x60D) registers.
  • Corrected order of TX_PFC_SADDRH (offset 0x610) and TX_PFC_SADDRL (offset 0x60F) registers.
  • Corrected description of RX_PAUSE_DADDR registers at offsets 0x707 and 0x708. These registers are the same for standard flow control and for priority-based flow control.
  • Corrected installation directory figure for Stratix V variations, in Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices.
  • Corrected erroneous indication that the value in RETRANSMIT_XOFF_HOLDOFF_EN at offset 0x607 is indexed by the value in the TX_PAUSE_QNUMBER register. In fact, the RETRANSMIT_XOFF_HOLDOFF_EN register includes one bit for every flow-control priority queue (one bit in case of standard flow control). Change is in Pause Registers section.
  • Fixed assorted typos and minor errors.
2014.08.18 14.0 and 14.0 Arria 10 Edition
  • Updated for new Quartus II IP Catalog, which replaces the MegaWizard Plug-In Manager starting in the Quartus II sofware v14.0. Changes are located primarily in Getting Started chapter. Reordered the chapter to accommodate the new descriptions.
  • Updated the Installation section to clarify that the LL 40-100GbE IP core v14.0 is available from the Self-Service Licensing Center, and the LL 40-100GbE IP core v14.0 Arria 10 Edition is included in the Quartus II software installation.
  • Added new, additional allowed value for PHY reference clock frequency: 322.265625 MHz.
  • Added new parameter option to configure an inter-packet gap of 8.
  • Added new parameter option to configure the IP core without adapters, exposing a custom streaming client interface that is narrower than the Avalon-ST interface. This option is available in IP cores configured without a 1588 PTP module and without an internal flow control scheme. You must select the custom streaming client interface or the Avalon-ST client interface. Your selection applies to both the RX and TX client interfaces.
  • Added new parameter option to configure priority-based flow control. This option is available in 100GbE variations with Tx CRC insertion turned on and with an Avalon-ST client interface.
    • Adds a new parameter to specify between 1 and 8 priority queues, inclusive.
    • Expands the width of the pause signals to the number of priority queues. Each bit refers to the corresponding priority queue.
    • Modifies the pause registers to apply to both standard and priority-based flow control. In some cases the register fields do not change and in others the register field widens to one bit per priority queue. In the case of three registers, modifies them drastically so they are essentially different registers in the case of priority-based flow control:
      • TX_XOF_EN at offset 0x60A has no equivalent register in priority-based flow control. The replacement register at this offset, TX_PAUSE_QNUMBER, holds the queue number of the queue to which the current contents of the RETRANSMIT_XOFF_HOLDOFF_EN, RETRANSMIT_XOFF_HOLDOFF_QUANTA, and TX_PAUSE_QUANTA apply.
      • RX_PAUSE_DADDR1 and RX_PAUSE_DADDR0 are replaced with RX_PFC_DADDRH and RX_PFC_DADDRL, which divide the 48-bit destination address for matching differently than the standard flow-control registers.
    • Adds new pause registers CFG_RETRANSMIT_EN, CFG_RETRANSMIT_QUANTA, TX_PFC_DADDRH, TX_PFC_DADDRL, TX_PFC_SADDRH, and TX_PFC_SADDRL.
  • Stratix V variations no longer support an internal transceiver reconfiguration controller. User logic must instantiate a transceiver reconfiguration controller.
    • Removed registers at offsets 0x350, 0x351, 0x352, and 0x353.
    • Added signals reconfig_from_xcvr, reconfig_to_xcvr, and reconfig_busy in Stratix V variations.
  • Updated Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v14.1 appendix with new Low Latency 40-100GbE IP core features.
  • Updated description of example project to clarify the Arria 10 project no longer implements additional input clocks to demonstrate static timing derivation.
  • Added instructions to generate the testbench and example project in the 14.0 and 14.0 Arria 10 Edition versions of the IP core.
  • Reorganized the testbench sections of Chapter 2, Getting Started.
  • Corrected addresses of the following statistics registers:
    • CNTR_TX_CRCERR registers from 0x804-0x805 to 0x806-0x807.
    • CNTR_TX_FCS registers from 0x806-0x807 to 0x804-0x805
    • CNTR_RX_CRCERR registers from 0x904-0x8905 to 0x906-0x907.
    • CNTR_RX_FCS registers from 0x906-0x907 to 0x904-0x905
  • Corrected direction of clk_txmac and clk_rxmac in table in Signals section to Output.
  • Added HW reset values for PHY registers that have them. All PHY register listings except those for the identifier string registers and the frequency registers now list a HW reset value.
  • Added basic information to description of HI BER field of PHY_RXPCS_STATUS register.

2014.04.28

13.1 Update 3

13.1 Arria 10 Edition Update 2

  • Corrected presentation of resource utilization numbers for Stratix V device family to clarify size of IP core without 1588 PTP module
  • Renamed Pause Registers tables to Ethernet Flow Control (Pause Functionality) Registers for consistency
  • In Low Latency 40-100GbE IP Core Address Map table, clarified that the 1588 PTP registers are only available if you turn on the parameter to include the 1588 PTP module in your IP core instance. The same information was already available in the table for other registers that are only available if you turn on the associated parameter.
  • Fixed assorted typos (column width in TX MAC Configuration Registers table, reset value widths of RX_PAUSE_DADDR0 register in RX Ethernet Flow Control Registers table and of TX_PTP_CLOCK_PERIOD register in TX 1588 PTP Registers table)

2014.04.11

13.1 Update 3

13.1 Arria 10 Edition Update 2

  • Added resource utilization numbers for Stratix V device family.
  • Corrected supported Stratix V device speed grade information for Low Latency 100GbE IP cores.
  • Added note to supported Stratix V device speed grade information table clarifying that Quartus II seed sweeping might be required for variations that include a 1588 PTP module to achieve a comfortable timing margin.

2014.03.06

13.1 Update 3

13.1 Arria 10 Edition Update 2

  • Corrected descriptions of pause enable registers:
    • Added description for TX_XOF_EN register at offset 0x60A.
    • Enhanced description of cfg_enable field of RX_PAUSE_ENABLE register at offset 0x705 to clarify the different functions of the TX_XOF_EN and RX_PAUSE_ENABLE registers in enabling the IP core to incoming pause frames.
    • Enhanced description of the TX_PAUSE_EN register at offset 0x605 to clarify the different functions of the TX_XOF_EN and TX_PAUSE_EN registers.
  • In "Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v13.1", enhanced the description of the differences in pause frame control and processing and in use of maximum frame size register information.
  • Updated "Congestion and Flow Control Using Pause Frames" with the enable register field information.
  • Updated "Pause Control Frame Filtering" with the new enable register field information and to clarify that by default, RX pause frame processing is enabled.
  • Enhanced "Low Latency 40-100GbE Example Project" to clarify that some project aspects are relevant only for Arria 10 devices.
  • Corrected "Clocks" section to include tx_serial_clk input clocks and to list clk_rxmac and clk_txmac as output clocks.

2014.02.17

13.1 Update 3

13.1 Arria 10 Edition Update 2

Initial release.

Level Two Title