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2.1. Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices
2.2. Licensing IP Cores
2.3. Specifying the Low Latency 40-100GbE IP Core Parameters and Options
2.4. IP Core Parameters
2.5. Files Generated for Stratix V Variations
2.6. Files Generated for Arria 10 Variations
2.7. Integrating Your IP Core in Your Design
2.8. Low Latency 40-100GbE IP Core Testbenches
2.9. Simulating the Low Latency 40‑100GbE IP Core With the Testbenches
2.10. Compiling the Full Design and Programming the FPGA
2.11. Initializing the IP Core
2.7.1. Pin Assignments
2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs
2.7.3. Transceiver PLL Required in Arria 10 Designs
2.7.4. External Time-of-Day Module for Variations with 1588 PTP Feature
2.7.5. Clock Requirements for 40GBASE-KR4 Variations
2.7.6. External TX MAC PLL
2.7.7. Placement Settings for the Low Latency 40-100GbE IP Core
2.9.1. Generating the Low Latency 40-100GbE Testbench
2.9.2. Optimizing the Low Latency 40‑100GbE IP Core Simulation With the Testbenches
2.9.3. Simulating with the Modelsim Simulator
2.9.4. Simulating with the NCSim Simulator
2.9.5. Simulating with the VCS Simulator
2.9.6. Testbench Output Example: Low Latency 40-100GbE IP Core
3.2.1. Low Latency 40-100GbE IP Core TX Datapath
3.2.2. Low Latency 40-100GbE IP Core TX Data Bus Interfaces
3.2.3. Low Latency 40-100GbE IP Core RX Datapath
3.2.4. Low Latency 40-100GbE IP Core RX Data Bus Interface
3.2.5. Low Latency 100GbE CAUI–4 PHY
3.2.6. External Reconfiguration Controller
3.2.7. External Transceiver PLL
3.2.8. External TX MAC PLL
3.2.9. Congestion and Flow Control Using Pause Frames
3.2.10. Pause Control and Generation Interface
3.2.11. Pause Control Frame Filtering
3.2.12. Link Fault Signaling Interface
3.2.13. Statistics Counters Interface
3.2.14. 1588 Precision Time Protocol Interfaces
3.2.15. PHY Status Interface
3.2.16. Transceiver PHY Serial Data Interface
3.2.17. Low Latency 40GBASE-KR4 IP Core Variations
3.2.18. Control and Status Interface
3.2.19. Arria 10 Transceiver Reconfiguration Interface
3.2.20. Clocks
3.2.21. Resets
3.2.2.1. Low Latency 40-100GbE IP Core User Interface Data Bus
3.2.2.2. Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)
3.2.2.3. Low Latency 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface)
3.2.2.4. Bus Quantization Effects With Adapters
3.2.2.5. User Interface to Ethernet Transmission
3.2.3.1. Low Latency 40-100GbE IP Core RX Filtering
3.2.3.2. 40-100GbE IP Core Preamble Processing
3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal
3.2.3.4. 40-100GbE IP Core CRC Checking
3.2.3.5. LL 40-100GbE IP Core Malformed Packet Handling
3.2.3.6. RX CRC Forwarding
3.2.3.7. Inter-Packet Gap
3.2.3.8. Pause Ignore
3.2.3.9. Control Frame Identification
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3.2. Low Latency 40-100GbE MAC and PHY Functional Description
The Altera Low Latency 40‑100GbE IP core implements the 40‑100GbE Ethernet MAC in accordance with the IEEE 802.3ba 2010 40G and 100G Ethernet Standard. This IP core handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 40‑100GbE Ethernet PCS and PMA (PHY).
In the transmit direction, the MAC accepts client frames, and inserts inter-packet gap (IPG), preamble, start of frame delimiter (SFD), padding, and CRC bits before passing them to the PHY. The PHY encodes the MAC frame as required for reliable transmission over the media to the remote end.
In the receive direction, the PHY passes frames to the MAC. The MAC accepts frames from the PHY, performs checks, updates statistics counters, strips out the CRC, preamble, and SFD, and passes the rest of the frame to the client. In RX preamble pass-through mode, the MAC passes on the preamble and SFD to the client instead of stripping them out. In RX CRC pass-through mode (bit 1 of the CRC_CONFIG register has the value of 1), the MAC passes on the CRC bytes to the client and asserts the EOP signal in the same clock cycle with the final CRC byte.
The Low Latency 40-100GbE IP core includes the following interfaces:
- Datapath client-interface–The following options are available:
- 40GbE with adapters—Avalon‑ST, 256 bits
- 40GbE—Custom streaming, 128 bits
- 100GbE with adapters—Avalon‑ST, 512 bits
- 100GbE—Custom streaming, 256 bits
- Management interface—Avalon-MM host slave interface for MAC management. This interface has a data width of 32 bits and an address width of 16 bits.
- Datapath Ethernet interface–The following options are available:
- 40GbE—Four 10.3125 Gbps serial links
- 100GbE—Ten 10.3125 Gbps serial links
- 100GbE CAUI–4—Four 25.78125 Gbps serial links
- In Arria 10 variations, an Arria 10 dynamic reconfiguration interface—an Avalon-MM interface to read and write the Arria 10 Native PHY IP core registers. This interface supports dynamic reconfiguration of the transceiver. Low Latency 40-100GbE IP cores that target an Arria 10 device use the Arria 10 Native PHY IP core to configure the Ethernet link serial transceivers on the device. This interface has a data width of 32 bits. This interface has an address width of 12 bits for 40GbE and 100GbE CAUI-4 variations, and an address width of 14 bits for standard 100GbE variations.
Section Content
Low Latency 40-100GbE IP Core TX Datapath
Low Latency 40-100GbE IP Core TX Data Bus Interfaces
Low Latency 40-100GbE IP Core RX Datapath
Low Latency 40-100GbE IP Core RX Data Bus Interface
Low Latency 100GbE CAUI–4 PHY
External Reconfiguration Controller
External Transceiver PLL
External TX MAC PLL
Congestion and Flow Control Using Pause Frames
Pause Control and Generation Interface
Pause Control Frame Filtering
Link Fault Signaling Interface
Statistics Counters Interface
1588 Precision Time Protocol Interfaces
PHY Status Interface
Transceiver PHY Serial Data Interface
Low Latency 40GBASE-KR4 IP Core Variations
Control and Status Interface
Arria 10 Transceiver Reconfiguration Interface
Clocks
Resets