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2.1. Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices
2.2. Licensing IP Cores
2.3. Specifying the Low Latency 40-100GbE IP Core Parameters and Options
2.4. IP Core Parameters
2.5. Files Generated for Stratix V Variations
2.6. Files Generated for Arria 10 Variations
2.7. Integrating Your IP Core in Your Design
2.8. Low Latency 40-100GbE IP Core Testbenches
2.9. Simulating the Low Latency 40‑100GbE IP Core With the Testbenches
2.10. Compiling the Full Design and Programming the FPGA
2.11. Initializing the IP Core
2.7.1. Pin Assignments
2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs
2.7.3. Transceiver PLL Required in Arria 10 Designs
2.7.4. External Time-of-Day Module for Variations with 1588 PTP Feature
2.7.5. Clock Requirements for 40GBASE-KR4 Variations
2.7.6. External TX MAC PLL
2.7.7. Placement Settings for the Low Latency 40-100GbE IP Core
2.9.1. Generating the Low Latency 40-100GbE Testbench
2.9.2. Optimizing the Low Latency 40‑100GbE IP Core Simulation With the Testbenches
2.9.3. Simulating with the Modelsim Simulator
2.9.4. Simulating with the NCSim Simulator
2.9.5. Simulating with the VCS Simulator
2.9.6. Testbench Output Example: Low Latency 40-100GbE IP Core
3.2.1. Low Latency 40-100GbE IP Core TX Datapath
3.2.2. Low Latency 40-100GbE IP Core TX Data Bus Interfaces
3.2.3. Low Latency 40-100GbE IP Core RX Datapath
3.2.4. Low Latency 40-100GbE IP Core RX Data Bus Interface
3.2.5. Low Latency 100GbE CAUI–4 PHY
3.2.6. External Reconfiguration Controller
3.2.7. External Transceiver PLL
3.2.8. External TX MAC PLL
3.2.9. Congestion and Flow Control Using Pause Frames
3.2.10. Pause Control and Generation Interface
3.2.11. Pause Control Frame Filtering
3.2.12. Link Fault Signaling Interface
3.2.13. Statistics Counters Interface
3.2.14. 1588 Precision Time Protocol Interfaces
3.2.15. PHY Status Interface
3.2.16. Transceiver PHY Serial Data Interface
3.2.17. Low Latency 40GBASE-KR4 IP Core Variations
3.2.18. Control and Status Interface
3.2.19. Arria 10 Transceiver Reconfiguration Interface
3.2.20. Clocks
3.2.21. Resets
3.2.2.1. Low Latency 40-100GbE IP Core User Interface Data Bus
3.2.2.2. Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)
3.2.2.3. Low Latency 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface)
3.2.2.4. Bus Quantization Effects With Adapters
3.2.2.5. User Interface to Ethernet Transmission
3.2.3.1. Low Latency 40-100GbE IP Core RX Filtering
3.2.3.2. 40-100GbE IP Core Preamble Processing
3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal
3.2.3.4. 40-100GbE IP Core CRC Checking
3.2.3.5. LL 40-100GbE IP Core Malformed Packet Handling
3.2.3.6. RX CRC Forwarding
3.2.3.7. Inter-Packet Gap
3.2.3.8. Pause Ignore
3.2.3.9. Control Frame Identification
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2.8. Low Latency 40-100GbE IP Core Testbenches
Altera provides a testbench , a hardware design example, and a compilation-only example design with most variations of the Low Latency 40-100GbE IP core. The testbench is available for simulation of your IP core, and the hardware design example can be run on hardware. You can run the testbench to observe the IP core behavior on the various interfaces in simulation.
Altera offers testbenches for all Avalon-ST client interface variations that generate their own TX MAC clock(Use external TX MAC PLL is turned off).
Currently, the IP core can generate a testbench and example project for variations that use an external TX MAC PLL, but these testbenches and example projects do not function correctly. Non-functional testbenches and example projects provide an example of the connections you must create in your design to ensure the LL 40-100GbE IP core functions correctly. However, you cannot simulate them nor run them in hardware.
To generate the testbench, in the Low Latency 40-100GbE parameter editor, you must first set the parameter values for the IP core variation you intend to generate. If you do not set the parameter values identically, the testbench you generate might not exercise the IP core variation you generate. If your IP core variation does not meet the criteria for a testbench, the generation process does not create a testbench (with the exception of the non-functional testbench generated if an IP core requires an external TX MAC clock signal).
You can simulate the testbench that you generate with your IP core variation. The testbench illustrates packet traffic, in addition to providing information regarding the transceiver PHY. The 40GBASE-KR4 testbench exercises auto-negotiation and link training, in addition to generating and checking packet traffic.