Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

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ID 683628
Date 12/28/2017
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Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core 2. Getting Started 3. Functional Description 4. Debugging the Link A. Arria 10 10GBASE-KR Registers B. Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.1 C. Additional Information
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core x
1.1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features 1.2. Low Latency 40-100GbE IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. Low Latency 40-100GbE IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. Low Latency 40-100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Stratix V Resource Utilization for Low Latency 40-100GbE IP Cores 1.4.2. Arria 10 Resource Utilization for Low Latency 40-100GbE IP Cores
2. Getting Started x
2.1. Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices 2.2. Licensing IP Cores 2.3. Specifying the Low Latency 40-100GbE IP Core Parameters and Options 2.4. IP Core Parameters 2.5. Files Generated for Stratix V Variations 2.6. Files Generated for Arria 10 Variations 2.7. Integrating Your IP Core in Your Design 2.8. Low Latency 40-100GbE IP Core Testbenches 2.9. Simulating the Low Latency 40‑100GbE IP Core With the Testbenches 2.10. Compiling the Full Design and Programming the FPGA 2.11. Initializing the IP Core
2.2. Licensing IP Cores x
2.2.1. OpenCore Plus IP Evaluation
2.7. Integrating Your IP Core in Your Design x
2.7.1. Pin Assignments 2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.7.3. Transceiver PLL Required in Arria 10 Designs 2.7.4. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.5. Clock Requirements for 40GBASE-KR4 Variations 2.7.6. External TX MAC PLL 2.7.7. Placement Settings for the Low Latency 40-100GbE IP Core
2.8. Low Latency 40-100GbE IP Core Testbenches x
2.8.1. Low Latency 40-100GbE IP Core Testbench Overview 2.8.2. Understanding the Testbench Behavior
2.9. Simulating the Low Latency 40‑100GbE IP Core With the Testbenches x
2.9.1. Generating the Low Latency 40-100GbE Testbench 2.9.2. Optimizing the Low Latency 40‑100GbE IP Core Simulation With the Testbenches 2.9.3. Simulating with the Modelsim Simulator 2.9.4. Simulating with the NCSim Simulator 2.9.5. Simulating with the VCS Simulator 2.9.6. Testbench Output Example: Low Latency 40-100GbE IP Core
3. Functional Description x
3.1. High Level System Overview 3.2. Low Latency 40-100GbE MAC and PHY Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. Low Latency 40-100GbE MAC and PHY Functional Description x
3.2.1. Low Latency 40-100GbE IP Core TX Datapath 3.2.2. Low Latency 40-100GbE IP Core TX Data Bus Interfaces 3.2.3. Low Latency 40-100GbE IP Core RX Datapath 3.2.4. Low Latency 40-100GbE IP Core RX Data Bus Interface 3.2.5. Low Latency 100GbE CAUI–4 PHY 3.2.6. External Reconfiguration Controller 3.2.7. External Transceiver PLL 3.2.8. External TX MAC PLL 3.2.9. Congestion and Flow Control Using Pause Frames 3.2.10. Pause Control and Generation Interface 3.2.11. Pause Control Frame Filtering 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. 1588 Precision Time Protocol Interfaces 3.2.15. PHY Status Interface 3.2.16. Transceiver PHY Serial Data Interface 3.2.17. Low Latency 40GBASE-KR4 IP Core Variations 3.2.18. Control and Status Interface 3.2.19. Arria 10 Transceiver Reconfiguration Interface 3.2.20. Clocks 3.2.21. Resets
3.2.1. Low Latency 40-100GbE IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter‑Packet Gap Generation and Insertion 3.2.1.7. Error Insertion Test and Debug Feature
3.2.2. Low Latency 40-100GbE IP Core TX Data Bus Interfaces x
3.2.2.1. Low Latency 40-100GbE IP Core User Interface Data Bus 3.2.2.2. Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. Low Latency 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. Order of Transmission
3.2.3. Low Latency 40-100GbE IP Core RX Datapath x
3.2.3.1. Low Latency 40-100GbE IP Core RX Filtering 3.2.3.2. 40-100GbE IP Core Preamble Processing 3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. 40-100GbE IP Core CRC Checking 3.2.3.5. LL 40-100GbE IP Core Malformed Packet Handling 3.2.3.6. RX CRC Forwarding 3.2.3.7. Inter-Packet Gap 3.2.3.8. Pause Ignore 3.2.3.9. Control Frame Identification
3.2.4. Low Latency 40-100GbE IP Core RX Data Bus Interface x
3.2.4.1. Low Latency 40-100GbE IP Core User Interface Data Bus 3.2.4.2. Low Latency 40-100GbE IP Core RX Data Bus 3.2.4.3. Low Latency 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.9. Congestion and Flow Control Using Pause Frames x
3.2.9.1. Conditions Triggering XOFF Frame Transmission 3.2.9.2. Conditions Triggering XON Frame Transmission
3.2.13. Statistics Counters Interface x
3.2.13.1. OctetOK Count Interface
3.2.14. 1588 Precision Time Protocol Interfaces x
3.2.14.1. Implementing a 1588 System That Includes a LL 40-100GbE IP Core 3.2.14.2. PTP Receive Functionality 3.2.14.3. PTP Transmit Functionality 3.2.14.4. External Time-of-Day Module for 1588 PTP Variations 3.2.14.5. PTP Timestamp and TOD Formats 3.2.14.6. 1588 PTP Interface Signals
3.3. Signals x
3.3.1. Low Latency 40-100GbE IP Core Signals
3.4. Software Interface: Registers x
3.4.1. Low Latency 40-100GbE IP Core Registers 3.4.2. LL 40‑100GbE Hardware Design Example Registers
3.4.1. Low Latency 40-100GbE IP Core Registers x
3.4.1.1. PHY Registers 3.4.1.2. Link Fault Signaling Registers 3.4.1.3. LL 40GBASE-KR4 Registers 3.4.1.4. Low Latency 40-100GbE IP Core MAC Configuration Registers 3.4.1.5. Pause Registers 3.4.1.6. TX Statistics Registers 3.4.1.7. RX Statistics Registers 3.4.1.8. 1588 PTP Registers
3.4.2. LL 40‑100GbE Hardware Design Example Registers x
3.4.2.1. Packet Client Registers
4. Debugging the Link x
4.1. Creating a SignalTap II Debug File to Match Your Design Hierarchy
A. Arria 10 10GBASE-KR Registers x
A.1. 10GBASE-KR PHY Register Definitions
C. Additional Information x
C.1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Archives C.2. Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History C.3. How to Contact Altera C.4. Typographic Conventions
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core
2. Getting Started
3. Functional Description
4. Debugging the Link
A. Arria 10 10GBASE-KR Registers
B. Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.1
C. Additional Information

2.4. IP Core Parameters

The Low Latency 40-100GbE parameter editor provides the parameters you can set to configure the Low Latency 40-100GbE IP core and simulation and hardware design examples.

LL 40-100GbE IP core variations that target an Arria 10 device include an Example Design tab.

Table 8.   Low Latency 40-100GbE Parameters: Main TabDescribes the parameters for customizing the 40-100GbE IP core on the Main tab of the 40-100GbE parameter editor.

Parameter

Type

Range

Default Setting

Parameter Description

General Options

Device family

String

  • Stratix V
  • Arria 10

According to the setting in the project or IP Catalog settings.

Selects the device family.

Protocol speed

String

  • 40 GbE
  • 100 GbE

100 GbE

Selects the MAC datapath width.

Data interface

String

  • Custom–ST
  • Avalon–ST

Avalon–ST

Selects the Avalon–ST interface or the narrower, custom streaming client interface to the MAC.

If you select the custom streaming client interface, the Flow control mode and Enable 1588 PTP parameters are not available.

PCS/PMA Options

Enable CAUI4 PCS 1 2

Boolean

  • True
  • False

False

If turned on, the IP core is a 100GbE CAUI-4 variation, with four 25.78125 Gbps transceiver PHY links.

Enable SyncE

Boolean

  • True
  • False

False

Exposes the RX recovered clock as an output signal. This feature supports the Synchronous Ethernet standard described in the ITU-T G.8261, G.8262, and G.8264 recommendations.

This parameter is available only in variations that target an Arria 10 device.

PHY reference frequency

Integer (encoding)

  • 322.265625 MHz
  • 644.53125 MHz

644.53125 MHz

Sets the expected incoming PHY clk_ref reference frequency. The input clock frequency must match the frequency you specify for this parameter (± 100ppm).

Use external TX MAC PLL Boolean
  • True
  • False
 False If you turn this option on, the IP core is configured to expect an input clock to drive the TX MAC. The input clock signal is clk_txmac_in.

Flow Control Options

Flow control mode

String

  • No flow control
  • Standard flow control
  • Priority-based flow control

No flow control

Configures the flow control mechanism the IP core implements. Standard flow control is Ethernet standard flow control.

If you select the custom streaming client interface, the IP core must be configured with no flow control, and this parameter is not available.

Number of PFC queues

Integer

1–8

8

Number of distinct priority queues for priority-based flow control. This parameter is available only if you set Flow control mode to Priority-based flow control.

Average interpacket gap

String

  • Disable deficit idle counter
  • 8
  • 12

12

If you set the value of this parameter to 8 or to 12, the IP core includes a deficit idle counter (DIC), which maintains an average interpacket gap (IPG) of 8 or 12, as you specify. If you set the value of this parameter to Disable deficit idle counter, the IP core is configured without the DIC, and does not maintain the required minimum average IPG. The Ethernet standard requires a minimum average IPG of 12. Turning off Average interpacket gap increases bandwidth.

MAC Options

Enable 1588 PTP

Boolean

  • True
  • False

False

If turned on, the IP core supports the IEEE Standard 1588-2008 Precision Clock Synchronization Protocol, by providing the hooks to implement the Precise Timing Protocol (PTP).

If you select the custom streaming client interface, the IP core must be configured without 1588 support, and this parameter is not available.

Enable 96b Time of Day Format Boolean
  • True
  • False
True Include the 96-bit interface to the TOD module. If you turn on this parameter, the TOD module that is generated with the IP core has a matching 96-bit timestamp interface.

If Enable 1588 PTP is turned on, you must turn on at least one of Enable 96b Time of Day Format and Enable 64b Time of Day Format. You can turn on both Enable 96b Time of Day Format and Enable 64b Time of Day Format to generate a TOD interface for each format.

This parameter is available only in variations with Enable 1588 PTP turned on.

Enable 64b Time of Day Format Boolean
  • True
  • False
False Include the 64-bit interface to the TOD module. If you turn on this parameter, the TOD module that is generated with the IP core has a matching 64-bit timestamp interface.

If Enable 1588 PTP is turned on, you must turn on at least one of Enable 96b Time of Day Format and Enable 64b Time of Day Format. You can turn on both Enable 96b Time of Day Format and Enable 64b Time of Day Format to generate a TOD interface for each format.

This parameter is available only in variations with Enable 1588 PTP turned on.

Timestamp fingerprint width Integer 1–16 1 Specifies the number of bits in the fingerprint that the IP core handles.

This parameter is available only in variations with Enable 1588 PTP turned on.

Enable link fault generation

Boolean

  • True
  • False

False

If turned on, the IP core includes the link fault signaling modules and relevant signals. If turned off, the IP core is configured without these modules and without these signals. Turning on link fault signaling provides your design a tool to improve reliability, but increases resource utilization.

Enable TX CRC insertion

Boolean

  • True
  • False

True

If turned on, the IP core inserts a 32-bit Frame Check Sequence (FCS), which is a CRC-32 checksum, in outgoing Ethernet frames. If turned off, the IP core does not insert the CRC-32 sequence in outgoing Ethernet communication. Turning on TX CRC insertion improves reliability but increases resource utilization and latency through the IP core.

If you turn on flow control, the IP core must be configured with TX CRC insertion, and this parameter is not available.

Enable preamble passthrough

Boolean

  • True
  • False

False

If turned on, the IP core is in RX and TX preamble pass-through mode. In RX preamble pass-through mode, the IP core passes the preamble and SFD to the client instead of stripping them out of the Ethernet packet. In TX preamble pass-through mode, the client specifies the preamble to be sent in the Ethernet frame.

Enable alignment EOP on FCS word

Boolean

  • True
  • False

True

If turned on, the IP core aligns the 32-bit Frame Check Sequence (FCS) error signal with the assertion of the EOP by delaying the RX data bus to match the latency of the FCS computation. If turned off, the IP core does not delay the RX data bus to match the latency of the FCS computation. If the parameter is turned off, the FCS error signal, in the case of an FCS error, is asserted in a later clock cycle than the relevant assertion of the EOP signal.

Altera recommends that you turn on this option. Otherwise, the latency between the EOP indication and assertion of the FCS error signal is non-deterministic.

You must turn on this parameter if your design relies on the rx_inc_octetsOK signal..

Enable TX statistics

Boolean

  • True
  • False

True

If turned on, the IP core includes built–in TX statistics counters. If turned off, the IP core is configured without TX statistics counters. In any case, the IP core is configured with TX statistics counter increment output vectors.

Enable RX statistics

Boolean

  • True
  • False

True

If turned on, the IP core includes built–in RX statistics counters. If turned off, the IP core is configured without RX statistics counters. In any case, the IP core is configured with RX statistics counter increment output vectors.

Configuration, Debug and Extension Options

Enable Altera Debug Master Endpoint (ADME)

Boolean

  • True
  • False

False

If turned on, the IP core turns on the following features in the Arria 10 PHY IP core that is included in the LL 40-100GbE IP core:

  • Enable Altera Debug Master Endpoint (ADME)
  • Enable capability registers

If turned off, the IP core is configured without these features.

This parameter is available only in variations that target an Arria 10 device. For information about these Arria 10 features, refer to the Arria 10 Transceiver PHY User Guide.

Table 9.  LL 40-100GbE Parameters: 40GBASE-KR4 TabDescribes the parameters for customizing a 40GBASE-KR4 Low Latency 40-100GbE IP core, on the 40GBASE-KR4 tab of the LL 40-100GbE parameter editor. The parameters on this tab are available only if the following conditions hold:
  • Your IP core targets an Arria 10 device. You set the target device family for your Quartus Prime project or in the Quartus Prime software before you acess the IP Catalog.
  • You select the value of 40GbE for the Protocol speed parameter on the Main tab.
  • You turn off the Enable 1588 PTP parameter on the Main tab.

Parameter

Type

Range

Default Setting

Parameter Description

KR4 General Options

Enable KR4

Boolean

  • True
  • False

False

If this parameter is turned on, the IP core is a 40GBASE-KR4 variation. If this parameter is turned off, the IP core is not a 40GBASE-KR4 variation, and the other parameters on this tab are not available.

Status clock rate Frequency range 100–125 MHz 100 MHz Sets the expected incoming clk_status frequency. The input clock frequency must match the frequency you specify for this parameter.

The IP core is configured with this information:

  • To ensure the IP core measures the link fail inhibit time accurately. Determines the value of the Link Fail Inhibit timer (IEEE 802.3 clause 73.10.2) correctly.
  • If clk_status frequency is not 100 MHz, to adjust the PHY clock monitors to report accurate frequency information.

This parameter determines the PHY Management clock (MGMT_CLK) frequency in MHz parameter of the underlying 10GBASE-KR PHY IP core. However, the default value of the Status clock rate parameter is not identical to the default value of the PHY IP core PHY Management clock (MGMT_CLK) frequency in MHz parameter.

Auto-Negotiation

Enable Auto-Negotiation

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core includes logic to implement auto-negotiation as defined in Clause 73 of IEEE Std 802.3ap–2007. If this parameter is turned off, the IP core does not include auto-negotiation logic and cannot perform auto-negotiation.

Currently the IP core can only negotiate to KR4 mode.

Link fail inhibit time for 40Gb Ethernet

Integer (Unit: ms)

500–510 ms

504 ms

Specifies the time before link status is set to FAIL or OK. A link fails if the time duration specified by this parameter expires before link status is set to OK. For more information, refer to Clause 73 Auto-Negotiation for Backplane Ethernet in IEEE Standard 802.3ap–2007.

The 40GBASE-KR4 IP core asserts the rx_pcs_ready signal to indicate link status is OK.

Auto-Negotiation Master

String

  • Lane 0
  • Lane 1
  • Lane 2
  • Lane 3

Lane 0

Selects the master channel for auto-negotiation.

Pause ability–C0

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core indicates on the Ethernet link that it supports symmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2008.

Pause ability–C1

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core indicates on the Ethernet link that it supports asymmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2008.

Link Training: PMA Parameters

VMAXRULE

Integer

0–31 30

Specifies the maximum VOD. The default value, 60, represents 1200 mV.

VMINRULE

Integer

0–31 6

Specifies the minimum VOD. The default value, 9, represents 165 mV.

VODMINRULE

Integer

0–31 14

Specifies the minimum VOD for the first tap. The default value, 24, represents 440 mV.

VPOSTRULE

Integer

0–25 25

Specifies the maximum value that the internal algorithm for pre-emphasis will ever test in determining the optimum post-tap setting.

VPRERULE

Integer

0–16 16

Specifies the maximum value that the internal algorithm for pre-emphasis will ever test in determining the optimum pre-tap setting.

PREMAINVAL

Integer

0–31 30

Specifies the Preset VOD value. This value is set by the Preset command of the link training protocol, defined in Clause 72.6.10.2.3.1 of IEEE Std 802.3ap–2007.

PREPOSTVAL

Integer

0–25 0

Specifies the preset Post-tap value.

PREPREVAL

Integer

0–16 0

Specifies the preset Pre-tap value.

INITMAINVAL

Integer

0–31 25

Specifies the initial VOD value. This value is set by the Initialize command of the link training protocol, defined in Clause 72.6.10.2.3.2 of IEEE Std 802.3ap–2007.

INITPOSTVAL

Integer

0–25 13

Specifies the initial Post-tap value.

INITPREVAL

Integer

0–16 3

Specifies the initial Pre-tap value.

Link Training: General

Enable Link Training

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core includes the link training module, which configures the remote link partner TX PMD for the lowest Bit Error Rate (BER). LT is defined in Clause 72 of IEEE Std 802.3ap–2007.

Maximum bit error count

Integer

2n – 1 for n an integer in the range 4–10. 511

Specifies the maximum number of errors on a lane before the Link Training Error bit (40GBASE-KR4 register offset 0xD2, bit 4, 12, 20, or 28, depending on the lane) is set, indicating an unacceptable bit error rate.

n is the width of the Bit Error Counter that is configured in the IP core. The value to which you set this parameter determines n, and thus the width of the Bit Error Counter. Because the default value of this parameter is 511, the default width of the Bit Error Counter is 10 bits.

You can use this parameter to tune PMA settings. For example, if you see no difference in error rates between two different sets of PMA settings, you can increase the width of the bit error counter to determine if a larger counter enables you to distinguish between PMA settings.

Number of frames to send before sending actual data

Integer

  • 127
  • 255
127

Specifies the number of additional training frames the local link partner delivers to ensure that the link partner can correctly detect the local receiver state.

FEC Options

Include FEC sublayer

Boolean

  • True
  • False

False

If this parameter is turned on, the IP core includes logic to implement FEC

Set FEC_Ability bit on power up or reset

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core sets the FEC ability bit (40GBASE-KR4 register offset 0xB0, bit 16: KR FEC enable) on power up and reset.

This parameter is available if you turn on Include FEC sublayer.

Set FEC_Enable bit on power up or reset

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core sets the FEC enable bit (40GBASE-KR4 register offset 0xB0, bit 18: KR FEC request) on power up and reset. If you turn on this parameter but do not turn on Set FEC_ability bit on power up or reset, this parameter has no effect: the IP core cannot specify the value of 1 for FEC Requested without specifying the value of 1 for FEC Ability.

This parameter is available if you turn on Include FEC sublayer.

Table 10.   Low Latency 40-100GbE PHY Parameter SettingsLists the PHY parameters that are configured automatically based on parameter values you select in the Low Latency 40G/100G Ethernet parameter editor.

Parameter

40GbE Value

40GBASE-KR4 Value

100GbE Value

100GbE at CAUI–4

Lanes

4

10

4

Data rate per lane

10312.5 Mbps

10312.5 Mbps

25781.25 Mbps

Available PHY reference clock frequencies

322.265625 MHz

644.53125 MHz

322.265625 MHz

644.53125 MHz

322.265625 MHz

644.53125 MHz

Related Information
1 The Enable CAUI4 PCS parameter is disabled when Protocol speed is set to 100GbE and Device family is not Arria 10 , and when Protocol speed is set to 40GbE. If the parameter is disabled, the IP core is configured with the regular 100 Gbps PHY link option of 10 x 10.3125 Gbps.
2 For the Device family parameter, the CAUI-4 option requires the Arria 10 device.
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