Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
Visible to Intel only — GUID: nik1411172639503
Ixiasoft
Visible to Intel only — GUID: nik1411172639503
Ixiasoft
3.2.15. PHY Status Interface
The rx_pcs_ready output signal is available to provide status information to user logic. This signal is asserted when the RX lanes are fully aligned and ready to receive data.
The tx_lanes_stable output signal is available to provide status information to user logic. This signal is asserted when the TX lanes are fully aligned and ready to transmit data.