Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

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ID 683628
Date 12/28/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core 2. Getting Started 3. Functional Description 4. Debugging the Link A. Arria 10 10GBASE-KR Registers B. Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.1 C. Additional Information
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core x
1.1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features 1.2. Low Latency 40-100GbE IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. Low Latency 40-100GbE IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. Low Latency 40-100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Stratix V Resource Utilization for Low Latency 40-100GbE IP Cores 1.4.2. Arria 10 Resource Utilization for Low Latency 40-100GbE IP Cores
2. Getting Started x
2.1. Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices 2.2. Licensing IP Cores 2.3. Specifying the Low Latency 40-100GbE IP Core Parameters and Options 2.4. IP Core Parameters 2.5. Files Generated for Stratix V Variations 2.6. Files Generated for Arria 10 Variations 2.7. Integrating Your IP Core in Your Design 2.8. Low Latency 40-100GbE IP Core Testbenches 2.9. Simulating the Low Latency 40‑100GbE IP Core With the Testbenches 2.10. Compiling the Full Design and Programming the FPGA 2.11. Initializing the IP Core
2.2. Licensing IP Cores x
2.2.1. OpenCore Plus IP Evaluation
2.7. Integrating Your IP Core in Your Design x
2.7.1. Pin Assignments 2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.7.3. Transceiver PLL Required in Arria 10 Designs 2.7.4. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.5. Clock Requirements for 40GBASE-KR4 Variations 2.7.6. External TX MAC PLL 2.7.7. Placement Settings for the Low Latency 40-100GbE IP Core
2.8. Low Latency 40-100GbE IP Core Testbenches x
2.8.1. Low Latency 40-100GbE IP Core Testbench Overview 2.8.2. Understanding the Testbench Behavior
2.9. Simulating the Low Latency 40‑100GbE IP Core With the Testbenches x
2.9.1. Generating the Low Latency 40-100GbE Testbench 2.9.2. Optimizing the Low Latency 40‑100GbE IP Core Simulation With the Testbenches 2.9.3. Simulating with the Modelsim Simulator 2.9.4. Simulating with the NCSim Simulator 2.9.5. Simulating with the VCS Simulator 2.9.6. Testbench Output Example: Low Latency 40-100GbE IP Core
3. Functional Description x
3.1. High Level System Overview 3.2. Low Latency 40-100GbE MAC and PHY Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. Low Latency 40-100GbE MAC and PHY Functional Description x
3.2.1. Low Latency 40-100GbE IP Core TX Datapath 3.2.2. Low Latency 40-100GbE IP Core TX Data Bus Interfaces 3.2.3. Low Latency 40-100GbE IP Core RX Datapath 3.2.4. Low Latency 40-100GbE IP Core RX Data Bus Interface 3.2.5. Low Latency 100GbE CAUI–4 PHY 3.2.6. External Reconfiguration Controller 3.2.7. External Transceiver PLL 3.2.8. External TX MAC PLL 3.2.9. Congestion and Flow Control Using Pause Frames 3.2.10. Pause Control and Generation Interface 3.2.11. Pause Control Frame Filtering 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. 1588 Precision Time Protocol Interfaces 3.2.15. PHY Status Interface 3.2.16. Transceiver PHY Serial Data Interface 3.2.17. Low Latency 40GBASE-KR4 IP Core Variations 3.2.18. Control and Status Interface 3.2.19. Arria 10 Transceiver Reconfiguration Interface 3.2.20. Clocks 3.2.21. Resets
3.2.1. Low Latency 40-100GbE IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter‑Packet Gap Generation and Insertion 3.2.1.7. Error Insertion Test and Debug Feature
3.2.2. Low Latency 40-100GbE IP Core TX Data Bus Interfaces x
3.2.2.1. Low Latency 40-100GbE IP Core User Interface Data Bus 3.2.2.2. Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. Low Latency 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. Order of Transmission
3.2.3. Low Latency 40-100GbE IP Core RX Datapath x
3.2.3.1. Low Latency 40-100GbE IP Core RX Filtering 3.2.3.2. 40-100GbE IP Core Preamble Processing 3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. 40-100GbE IP Core CRC Checking 3.2.3.5. LL 40-100GbE IP Core Malformed Packet Handling 3.2.3.6. RX CRC Forwarding 3.2.3.7. Inter-Packet Gap 3.2.3.8. Pause Ignore 3.2.3.9. Control Frame Identification
3.2.4. Low Latency 40-100GbE IP Core RX Data Bus Interface x
3.2.4.1. Low Latency 40-100GbE IP Core User Interface Data Bus 3.2.4.2. Low Latency 40-100GbE IP Core RX Data Bus 3.2.4.3. Low Latency 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.9. Congestion and Flow Control Using Pause Frames x
3.2.9.1. Conditions Triggering XOFF Frame Transmission 3.2.9.2. Conditions Triggering XON Frame Transmission
3.2.13. Statistics Counters Interface x
3.2.13.1. OctetOK Count Interface
3.2.14. 1588 Precision Time Protocol Interfaces x
3.2.14.1. Implementing a 1588 System That Includes a LL 40-100GbE IP Core 3.2.14.2. PTP Receive Functionality 3.2.14.3. PTP Transmit Functionality 3.2.14.4. External Time-of-Day Module for 1588 PTP Variations 3.2.14.5. PTP Timestamp and TOD Formats 3.2.14.6. 1588 PTP Interface Signals
3.3. Signals x
3.3.1. Low Latency 40-100GbE IP Core Signals
3.4. Software Interface: Registers x
3.4.1. Low Latency 40-100GbE IP Core Registers 3.4.2. LL 40‑100GbE Hardware Design Example Registers
3.4.1. Low Latency 40-100GbE IP Core Registers x
3.4.1.1. PHY Registers 3.4.1.2. Link Fault Signaling Registers 3.4.1.3. LL 40GBASE-KR4 Registers 3.4.1.4. Low Latency 40-100GbE IP Core MAC Configuration Registers 3.4.1.5. Pause Registers 3.4.1.6. TX Statistics Registers 3.4.1.7. RX Statistics Registers 3.4.1.8. 1588 PTP Registers
3.4.2. LL 40‑100GbE Hardware Design Example Registers x
3.4.2.1. Packet Client Registers
4. Debugging the Link x
4.1. Creating a SignalTap II Debug File to Match Your Design Hierarchy
A. Arria 10 10GBASE-KR Registers x
A.1. 10GBASE-KR PHY Register Definitions
C. Additional Information x
C.1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Archives C.2. Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History C.3. How to Contact Altera C.4. Typographic Conventions
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core
2. Getting Started
3. Functional Description
4. Debugging the Link
A. Arria 10 10GBASE-KR Registers
B. Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.1
C. Additional Information

B. Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.1

The Low Latency 40-100GbE MegaCore function provides new functionality, and also sacrifices some dynamic configuration options and features to achieve low latency and lower resource utilization than the legacy 40-100GbE MegaCore function. In some cases, parameter options allow you to configure the Low Latency IP core to include or exclude features that are dynamically configurable in the legacy IP core, providing you the flexibility to achieve resource savings by removing features your design does not require.

To compare the Low Latency 40-100GbE MegaCore function to previous releases of the 40-100GbE MegaCore function, refer to the table and to the Altera documentation about the revision history of the legacy 40-100GbE MegaCore function.

Table 51.  Major Differences Between the Low Latency 40-100GbE IP Core v15.1 and the 40-100GbE IP Core v15.1

Lists the basic differences between the Altera 40- and 100-Gbps Ethernet MAC and PHY (40-100GbE) MegaCore function, a product available through several previous Altera software releases, and the Low Latency 40- and 100-Gbps Ethernet MAC and PHY (Low Latency 40-100GbE, or LL 40-100GbE) MegaCore function in its current release.

Property

Low Latency 40-100GbE IP Core

40-100GbE IP Core

IP core installation

IP core for Arria 10 devices is included in the Altera IP Library (included in the ACDS) installation

IP core for Stratix V devices is available for installation and integration into your ACDS installation from the Self-Service Licensing Center for releases 14.1, 15.0, and 15.1

IP core is included in the Altera IP Library

Device support

Supports Stratix V and Arria 10 device families. Altera recommends you target an Arria 10 device or use the 40-100GbE IP core instead.

Supports Stratix IV, Arria V GZ, and Stratix V device families.

Core options

MAC & PHY

PHY only, MAC only, or MAC & PHY

Duplex mode

Full duplex mode

RX-only, TX-only, or full duplex mode

MAC client interface

Avalon-ST interface or new, different custom streaming interface

Avalon-ST interface or custom streaming interface

CAUI–4 variations

Available for Arria 10 GT devices

Available for Stratix V GT devices

4 × 6.25 variations

Not currently available

Available for all supported devices

40GBASE-KR4 variations

Available for Arria 10 devices

Available for Stratix V devices

Statistics counters

RX statistics counters are configurable (turned on or off) in the parameter editor, and TX statistics counters are configurable in the parameter editor, with two separate parameters

Software clears all RX or all TX statistics counters at one time with a dedicated configuration register. Reading a statistics register does not affect its value.

RX and TX statistics counters are all available, or no statistics counters are available. Configurable in the parameter editor.

Programmable bits in MAC_CMD_CONFIG register determine whether reading a statistics register resets it to zero.

Statistics counter increment vectors

Available

Four additional RX statistics counter increment vectors and two new counters for number of bytes in non-errored RX frames and number of bytes in non-errored TX frames

Available

Synchronous Ethernet support

Available

Available

Preamble pass-through mode

Linked RX and TX preamble pass-through modes turned on or off in parameter editor. The RX and TX modes cannot be turned on or off individually and the mode cannot be dynamically configured.

RX and TX preamble pass-through modes individually dynamically configurable (programmable).

RX filtering

Programmable option to filter pause frames only

Programmable options for many RX filtering options, including destination address filtering

Maximum Ethernet frame size

Programmable maximum received frame size controls effect on the statistics increment vectors and statistics counters.

Programmable maximum received frame size controls oversized frame rejection and effect on the statistics increment vectors and statistics counters.Default maximum size is different for cut-through and store-and-forward modes.

Link fault signaling

Link fault signaling turned on or off in parameter editor. If link fault signaling is turned off, the relevant signals are not available.

If turned on, the IP core has a configurable option for IEEE 802.3 –2012 Ethernet Standard Clause 66 support.

The response in case of remote or local fault is determined by whether or not you turn on Clause 66 support.

Available. Programmable options to specify response to remote or local fault.

IEEE 802.3 –2012 Ethernet Standard Clause 66 support is not available.

TX FCS (CRC-32) insertion

Configurable in parameter editor.

Programmable in IP core registers.

Deficit idle counter (maintenance of minimum average 12-byte IPG)

Configurable in parameter editor. You can specify a minimum average IPG of 8 bytes or 12 bytes.

Always included.

More precise IPG control.

Available if you include the deficit idle counter.

Programmable in IP core registers.

RX FCS error flag alignment with EOP

Configurable in parameter editor. If alignment parameter is turned on, the RX FCS error flag is asserted in the same clock cycle with the EOP signal. If the parameter is turned off, the FCS error signal might be asserted in a later clock cycle.

If IP core detects an FCS error, RX FCS error flag is asserted in same clock cycle with the EOP signal, unless the IP core is in RX automatic pad removal mode. In RX automatic pad removal mode, the IP core might assert the two signals on different clock cycles.

RX automatic pad removal

Not available.

Programmable in IP core registers.

IEEE-1588 (PTP) support

Configurable in parameter editor.

Not available.

TX source address insertion

Not available. The IP core transmits the source address provided on the TX client interface in the source address field of the Ethernet frame.

Programmable in IP core registers.

Pause frame control and processing

You can request transmission of an XOFF or XON pause frame by asserting or deasserting a level input signal. You configure registers to specify the values in the pause frame.

For backward compatibility, you can also configure a register to request transmission of a pause frame. However, Altera recommends you make the request using the input signal instead.

Supports user-specified retransmission hold-off time, to specify the duration between repeat transmission of XOFF frames.

Pause frame address filtering of received pause frames compares the incoming pause frame destination address to the value in an IP core register.

Two independent enable register fields control the TX MAC processing of incoming pause frames on the Ethernet link and the response to a user pause request. A third enable register field controls the RX MAC processing of incoming pause frames on the Ethernet link.

In IP core variations without adapters, you can request transmission of an XOFF or XON pause frame by pulsing an edge-triggered input signal. Additional input signals specify the values in the pause frame. In all IP core MAC variations, you can request transmission and provide pause frame values by configuring registers.

Does not support retransmission hold-off time. You must control retransmission of XOFF frames in user logic. Asserting the edge-triggered input signal or setting the relevant pause request register field generates a single XOFF frame.

Pause frame address filtering of received pause frames compares the incoming pause frame destination address to the address of the IP core.

Two independent enable register fields control the IP core processing of incoming unicast and multicast pause frames on the Ethernet link. Does not support register control of IP core processing of incoming user pause requests. To avoid the IP core generating an outgoing pause frame in response to a user request, you must avoid generating user pause requests.

Priority-based flow control Configurable in parameter editor. Not available.

Reset

Single asynchronous reset signal resets the entire IP core. Additional reset signals reset the individual Avalon-MM interfaces: the control and status interface in all IP core variations, and the Arria 10 transceiver reconfiguration interface in IP core variations that target an Arria 10 device.

Five asynchronous reset signals reset individual components of the IP core. User must enforce recommended reset sequence.

Clocks

Input clocks for Avalon-MM interfaces and PLL reference clock.

PLL reference clock drives internal IP core clocks, and clk_rxmac and clk_txmac are output clocks.

Configurable option to provide TX MAC input clock from an external PLL or to include the PLL in the IP core. Clock signal from the external MAC PLL is a new input clock signal.

Input clocks for Avalon-MM interfaces, PLL reference clock, and RX and TX MAC (clk_rxmac and clk_txmac).

Stratix V transceiver dynamic reconfiguration controller

You must instantiate an external reconfiguration controller.

You must instantiate an external reconfiguration controller.

TX error insertion test and debug feature Available Not available
RX control frame status flags Available Not available
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