Cyclone V Device Handbook: Volume 2: Transceivers

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ID 683586
Date 10/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Transceiver Architecture in Cyclone V Devices 2. Transceiver Clocking in Cyclone V Devices 3. Transceiver Reset Control in Cyclone V Devices 4. Transceiver Protocol Configurations in Cyclone V Devices 5. Transceiver Custom Configurations in Cyclone V Devices 6. Transceiver Loopback Support 7. Dynamic Reconfiguration in Cyclone V Devices
1. Transceiver Architecture in Cyclone V Devices x
1.1. Architecture Overview 1.2. PMA Architecture 1.3. PCS Architecture 1.4. Channel Bonding 1.5. PLL Sharing 1.6. Document Revision History
1.1. Architecture Overview x
1.1.1. Transceiver Banks 1.1.2. 6.144 Gbps CPRI Support Capability in GT Devices 1.1.3. Transceiver Channel Architecture
1.1.1. Transceiver Banks x
1.1.1.1. Usage Restrictions on Specific Channels
1.2. PMA Architecture x
1.2.1. Transmitter PMA Datapath 1.2.2. Receiver PMA Datapath 1.2.3. Transmitter PLL 1.2.4. Clock Divider 1.2.5. Calibration Block
1.2.1. Transmitter PMA Datapath x
1.2.1.1. Serializer 1.2.1.2. Transmitter Buffer
1.2.1.1. Serializer x
1.2.1.1.1. Transmitter Polarity Inversion 1.2.1.1.2. Bit Reversal
1.2.1.2. Transmitter Buffer x
1.2.1.2.1. Transmitter Buffer Features and Capabilities 1.2.1.2.2. Programmable Transmitter Analog Settings 1.2.1.2.3. Programmable Transmitter VCM 1.2.1.2.4. Programmable Transmitter Differential OCT 1.2.1.2.5. Transmitter Protocol Specific
1.2.2. Receiver PMA Datapath x
1.2.2.1. Receiver Buffer 1.2.2.2. Deserializer
1.2.2.1. Receiver Buffer x
1.2.2.1.1. Programmable CTLE and DC Gain 1.2.2.1.2. Programmable Receiver VCM 1.2.2.1.3. Programmable Receiver Differential On-Chip Termination 1.2.2.1.4. Signal Threshold Detection Circuitry
1.2.2.2. Deserializer x
1.2.2.2.1. Clock-slip
1.2.3. Transmitter PLL x
1.2.3.1. Channel PLL Architecture 1.2.3.2. Channel PLL as CDR PLL 1.2.3.3. Channel PLL as a CMU PLL 1.2.3.4. fPLL as a Transmitter PLL
1.2.3.2. Channel PLL as CDR PLL x
1.2.3.2.1. Lock-to-Reference Mode 1.2.3.2.2. Lock-to-Data Mode 1.2.3.2.3. CDR PLL in Automatic Lock Mode 1.2.3.2.4. CDR PLL in Manual Lock Mode
1.3. PCS Architecture x
1.3.1. Transmitter PCS Datapath 1.3.2. Receiver PCS Datapath
1.3.1. Transmitter PCS Datapath x
1.3.1.1. Transmitter Phase Compensation FIFO 1.3.1.2. Byte Serializer 1.3.1.3. 8B/10B Encoder 1.3.1.4. Transmitter Bit-Slip
1.3.1.1. Transmitter Phase Compensation FIFO x
1.3.1.1.1. Registered Mode 1.3.1.1.2. Phase Compensation Mode
1.3.1.2. Byte Serializer x
1.3.1.2.1. Byte Serializer in Single-Width Mode 1.3.1.2.2. Byte Serializer in Double-Width Mode
1.3.1.3. 8B/10B Encoder x
1.3.1.3.1. 8B/10B Encoder in Single-Width Mode 1.3.1.3.2. 8B/10B Encoder in Double-Width Mode 1.3.1.3.3. Running Disparity Control 1.3.1.3.4. Control Code Encoding 1.3.1.3.5. Reset Condition 1.3.1.3.6. Encoder Output During Reset Sequence
1.3.2. Receiver PCS Datapath x
1.3.2.1. Word Aligner 1.3.2.2. Rate Match FIFO 1.3.2.3. 8B/10B Decoder 1.3.2.4. Byte Deserializer 1.3.2.5. Byte Ordering 1.3.2.6. Receiver Phase Compensation FIFO
1.3.2.1. Word Aligner x
1.3.2.1.1. Word Aligner Options and Behaviors 1.3.2.1.2. Word Aligner in Manual Alignment Mode 1.3.2.1.3. Word Aligner in Bit-Slip Mode 1.3.2.1.4. Word Aligner in Automatic Synchronization State Machine Mode 1.3.2.1.5. Word Aligner in Automatic Synchronization State Machine Mode with a 10-Bit PMA-PCS Interface Configuration 1.3.2.1.6. Word Aligner Operations in Deterministic Latency State Machine Mode 1.3.2.1.7. Programmable Run-Length Violation Detection 1.3.2.1.8. Receiver Polarity Inversion 1.3.2.1.9. Bit Reversal 1.3.2.1.10. Receiver Byte Reversal
1.3.2.3. 8B/10B Decoder x
1.3.2.3.1. 8B/10B Decoder in Single-Width Mode 1.3.2.3.2. 8B/10B Decoder in Double-Width Mode 1.3.2.3.3. Control Code Group Detection
1.3.2.4. Byte Deserializer x
1.3.2.4.1. Byte Deserializer in Single-Width Mode 1.3.2.4.2. Byte Deserializer in Double-Width Mode
1.3.2.5. Byte Ordering x
1.3.2.5.1. Byte Ordering in Single-Width Mode 1.3.2.5.2. Byte Ordering in Double-Width Mode 1.3.2.5.3. Word Aligner-Based Ordering Mode 1.3.2.5.4. Manual Ordering Mode
1.3.2.6. Receiver Phase Compensation FIFO x
1.3.2.6.1. Registered Mode
2. Transceiver Clocking in Cyclone V Devices x
2.1. Input Reference Clocking 2.2. Internal Clocking 2.3. FPGA Fabric–Transceiver Interface Clocking 2.4. Document Revision History
2.1. Input Reference Clocking x
2.1.1. Dedicated Reference Clock Pins 2.1.2. Fractional PLL (fPLL)
2.1.1. Dedicated Reference Clock Pins x
2.1.1.1. Dedicated refclk Using the Reference Clock Network 2.1.1.2. Dual-Purpose RX/refclk Pins
2.2. Internal Clocking x
2.2.1. Transmitter Clock Network 2.2.2. Transmitter Clocking 2.2.3. Receiver Clocking
2.2.2. Transmitter Clocking x
2.2.2.1. Non-Bonded Channel Configurations 2.2.2.2. Bonded Channel Configurations
2.2.3. Receiver Clocking x
2.2.3.1. Receiver Non-Bonded Channel Configurations 2.2.3.2. Receiver Bonded Channel Configurations
2.3. FPGA Fabric–Transceiver Interface Clocking x
2.3.1. Transceiver Datapath Interface Clocking 2.3.2. Transmitter Datapath Interface Clocking 2.3.3. Receiver Datapath Interface Clock
2.3.2. Transmitter Datapath Interface Clocking x
2.3.2.1. Quartus II-Software Selected Transmitter Datapath Interface Clock 2.3.2.2. Selecting a Transmitter Datapath Interface Clock
2.3.3. Receiver Datapath Interface Clock x
2.3.3.1. Quartus II Software-Selected Receiver Datapath Interface Clock 2.3.3.2. Selecting a Receiver Datapath Interface Clock
3. Transceiver Reset Control in Cyclone V Devices x
3.1. PHY IP Embedded Reset Controller 3.2. User-Coded Reset Controller 3.3. Transceiver Reset Using Avalon Memory Map Registers 3.4. Clock Data Recovery in Manual Lock Mode Resetting the Transceiver During Dynamic Reconfiguration 3.6. Transceiver Blocks Affected by the Reset and Powerdown Signals 3.7. Transceiver Power-Down 3.8. Document Revision History
3.1. PHY IP Embedded Reset Controller x
3.1.1. Embedded Reset Controller Signals 3.1.2. Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device Power-Up 3.1.3. Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device Operation
3.2. User-Coded Reset Controller x
3.2.1. User-Coded Reset Controller Signals 3.2.2. Resetting the Transmitter with the User-Coded Reset Controller During Device Power-Up 3.2.3. Resetting the Transmitter with the User-Coded Reset Controller During Device Operation 3.2.4. Resetting the Receiver with the User-Coded Reset Controller During Device Power-Up Configuration 3.2.5. Resetting the Receiver with the User-Coded Reset Controller During Device Operation
3.3. Transceiver Reset Using Avalon Memory Map Registers x
3.3.1. Transceiver Reset Control Signals Using Avalon Memory Map Registers
3.4. Clock Data Recovery in Manual Lock Mode x
3.4.1. Control Settings for CDR Manual Lock Mode 3.4.2. Resetting the Transceiver in CDR Manual Lock Mode
4. Transceiver Protocol Configurations in Cyclone V Devices x
4.1. PCI Express 4.2. Gigabit Ethernet 4.3. XAUI 4.4. Serial Digital Interface 4.5. Serial Data Converter (SDC) JESD204 4.6. SATA and SAS Protocols 4.7. Deterministic Latency Protocols—CPRI and OBSAI 4.8. Document Revision History
4.1. PCI Express x
4.1.1. PCIe Transceiver Datapath 4.1.2. PCIe Supported Features 4.1.3. PCIe Supported Configurations and Placement Guidelines
4.1.2. PCIe Supported Features x
4.1.2.1. PIPE Interface 4.1.2.2. Transmitter Electrical Idle Generation 4.1.2.3. Power State Management 4.1.2.4. 8B/10B Encoder Usage for Compliance Pattern Transmission Support 4.1.2.5. Receiver Status 4.1.2.6. Receiver Detection 4.1.2.7. Clock Rate Compensation Up to ±300 ppm 4.1.2.8. PCIe Reverse Parallel Loopback
4.2. Gigabit Ethernet x
4.2.1. Gigabit Ethernet Transceiver Datapath
4.3. XAUI x
4.3.1. Transceiver Datapath in a XAUI Configuration 4.3.2. XAUI Supported Features 4.3.3. Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration
4.4. Serial Digital Interface x
4.4.1. Configurations Supported in SDI Mode 4.4.2. Serial Digital Interface Transceiver Datapath
4.7. Deterministic Latency Protocols—CPRI and OBSAI x
4.7.1. Latency Uncertainty Removal with the Phase Compensation FIFO in Register Mode 4.7.2. Channel PLL Feedback for Deterministic Relationship 4.7.3. CPRI and OBSAI 4.7.4. 6.144-Gbps Support Capability in Cyclone V GT Devices 4.7.5. CPRI Enhancements
5. Transceiver Custom Configurations in Cyclone V Devices x
5.1. Standard PCS Configuration 5.2. Standard PCS in Low Latency Configuration 5.3. Document Revision History
5.1. Standard PCS Configuration x
5.1.1. Custom Configuration Channel Options 5.1.2. Rate Match FIFO in Custom Configuration
5.1.2. Rate Match FIFO in Custom Configuration x
5.1.2.1. Rate Match FIFO Behaviors in Custom Single-Width Mode 5.1.2.2. Rate Match FIFO Behaviors in Custom Double-Width Mode
5.2. Standard PCS in Low Latency Configuration x
5.2.1. Low Latency Custom Configuration Channel Options
6. Transceiver Loopback Support x
6.1. Serial Loopback 6.2. Forward Parallel Loopback 6.3. PIPE Reverse Parallel Loopback 6.4. Reverse Serial Loopback 6.5. Reverse Serial Pre-CDR Loopback 6.6. Document Revision History
7. Dynamic Reconfiguration in Cyclone V Devices x
7.1. Dynamic Reconfiguration Features 7.2. Offset Cancellation 7.3. Transmitter Duty Cycle Distortion Calibration 7.4. PMA Analog Controls Reconfiguration 7.5. Dynamic Reconfiguration of Loopback Modes 7.6. Transceiver PLL Reconfiguration 7.7. Transceiver Channel Reconfiguration 7.8. Transceiver Interface Reconfiguration 7.9. Reduced .mif Reconfiguration 7.10. Unsupported Reconfiguration Modes 7.11. Document Revision History
1. Transceiver Architecture in Cyclone V Devices
2. Transceiver Clocking in Cyclone V Devices
3. Transceiver Reset Control in Cyclone V Devices
4. Transceiver Protocol Configurations in Cyclone V Devices
5. Transceiver Custom Configurations in Cyclone V Devices
6. Transceiver Loopback Support
7. Dynamic Reconfiguration in Cyclone V Devices

2.2.1. Transmitter Clock Network

The transmitter PLL is comprised of the CMU PLL. All CMU PLLs are identical, but the usage varies depending on channel location due to the availability of access to the clock distribution network.
Table 33.   Usage Capability of Each CMU PLL Within Two Transceiver Banks
CMU PLL Location in Two Transceiver Banks Clock Network Access Usage Capability
CH 0 No Clock transmitter within same channel only
CH 1 Yes Clock transmitter within same channel only and other channels via clock network
CH 2 No Clock transmitter within same channel only
CH 3 No Clock transmitter within same channel only
CH 4 Yes Clock transmitter within same channel and other channels via clock network
CH 5 No Clock transmitter within same channel only

The transmitter clock network routes the clock from the transmitter PLL to the transmitter channel. As shown in the previous figure, the transmitter clock network routes the clock from the transmit PLL to the transmitter channel. A clock divider provides two clocks to the transmitter channel:

  • Serial clock—high-speed clock for the serializer
  • Parallel clock—low-speed clock for the serializer and the PCS

Cyclone V transceivers support non-bonded and bonded transceiver clocking configurations:

  • Non-bonded configuration—Only the serial clock from the transmit PLL is routed to the transmitter channel. The clock divider of each channel generates the local parallel clock.
  • Bonded configuration—Both the serial clock and parallel clock are routed from the central clock divider in channel 1 or 4 to the bonded transmitter channels.

The transmitter clock network is comprised of x1 (x1 and x1_fPLL), x6 and xN clock lines.

Table 34.  Characteristics of x1, x6, and xN Clock Lines
Characteristics x1 x1_fPLL x6 xN
Clock Source CMU PLL from CH 1 or CH 4 in two banks (serial clock only) fPLL adjacent to transceivers (serial clock only) Central clock divider from CH 1 or Ch 4 in two banks (serial and parallel clock ) x6 clock lines (serial and parallel clock)
Maximum Data Rate (Gbps) 5.0 (GT and ST), 3.125 (GX and SX) 3.125 5.0 (GT and ST), 3.125 (GX and SX) 3.125
Clock Line Span Within two transceiver banks Within a group of 3 channels (0, 1, 2 or 3, 4, 5) Within two transceiver banks Across all channels on the same side of the device
Non-bonded Configuration Yes Yes Yes Yes
Bonded Configuration No No Yes Yes
Figure 40.  x1 Clock Line Architecture


The x1 clock lines are driven by serial clocks of CMU PLLs from channels 1 and 4. The serial clock in the x1 clock line is then distributed to the local and central clock dividers of every channel within both the neighboring transceiver banks.

Note: When you configure the channel PLL as a CMU PLL to drive the local clock divider, or the central clock divider of its own channel, you cannot use the channel PLL as a CDR. Without a CDR, you can use the channel only as a transmitter channel.
Figure 41.  x6 and xN Clock Line Architecture


The x6 clock lines are driven by serial and parallel clocks from the central clock divider in channels 1 and 4. For channels 0 to 5 within the 2 transceiver banks, the serial and parallel clocks in the x6 clock line are then distributed to every channel in both the transceiver banks.

The xN clock lines extend the clocking reach of the x6 clock line to all channels on the same side of the device. To reach a xN clock line, the clocks must be provided on the x6 clock line. The serial and parallel clocks in the x6 clock line are distributed to every channel within the two transceiver banks. The serial and parallel clocks are distributed to other channels beyond the two banks or the six channels using the xN clock line.

In bonded configurations, serial and parallel clocks from the x6 or xN clock lines are received by the clock divider of every bonded channel and fed directly to the serializer. In a non-bonded configuration, the clock divider of every non-bonded channel receives the serial clock from the x6 or xN clock lines and generates the individual parallel clock to the serializer.

Note: In a bonded configuration, bonded channels must be placed contiguously without leaving a gap between the channels, except when the gap channel is a CMU PLL used for the bonded channels. The contiguous channels may span across many banks for bonded mode. For example, in x8 bonding, the bonded channels may span across 3 to 4 banks with the condition that there must be no gap between the channels except when the gap is due to the channel used for CMU PLL.
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