Visible to Intel only — GUID: nik1409855279118
Ixiasoft
Visible to Intel only — GUID: nik1409855279118
Ixiasoft
1.3.2.4. Byte Deserializer
The byte deserializer supports operation in single- and double-width modes. The datapath clock rate at the input of the byte deserializer is twice the FPGA fabric–receiver interface clock frequency. After byte deserialization, the word alignment pattern may be ordered in the MSByte or LSByte position.
The data is assumed to be received as LSByte first—the least significant 8 or 10 bits in single-width mode or the least significant 16 or 20 bits in double-width mode.
Mode | Byte Deserializer Input Datapath Width | Receiver Output Datapath Width |
---|---|---|
Single Width | 8 | 16 |
10 | 20 | |
Double Width | 16 | 32 |
20 | 40 |