Intel® FPGA Temperature Sensor IP Core User Guide

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ID 683585
Date 5/30/2018
Public
Document Table of Contents
Document Table of Contents x
Intel® FPGA Temperature Sensor IP Core User Guide
Intel® FPGA Temperature Sensor IP Core User Guide x
Intel® FPGA Temperature Sensor Features Intel® FPGA Temperature Sensor Functional Description Using Clear Box Generator Intel® FPGA Temperature Sensor Device Support Intel® FPGA Temperature Sensor Parameters Transfer Function for Internal TSD Intel® FPGA Temperature Sensor IP Core Signals Intel® FPGA Temperature Sensor Prototypes and Component Declarations Document Revision History
Intel® FPGA Temperature Sensor Functional Description x
Temperature Sensing Operation for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices Temperature Sensing Operation for Arria® V, Arria® V GZ, Stratix® V, and Stratix® IV Devices
Temperature Sensing Operation for Arria® V, Arria® V GZ, Stratix® V, and Stratix® IV Devices x
Generating the Intel® FPGA Temperature Sensor IP Core Example Design Compiling the Intel® FPGA Temperature Sensor IP Core Example Design
Intel® FPGA Temperature Sensor Prototypes and Component Declarations x
Verilog HDL Prototype VHDL Component Declaration
Intel® FPGA Temperature Sensor IP Core User Guide

Using Clear Box Generator

You can use clear box generator, a command-line executable, to configure parameters that are in the Intel® FPGA Temperature Sensor IP core parameter editor. The clear box generator creates or modifies custom IP core variations, which you can instantiate in a design file. The clear box generator generates IP core variation file in Verilog HDL or VHDL format.
Note: Intel® Arria® 10 and Intel® Cyclone® 10 GX Intel® FPGA Temperature SensorIP core do not support clear box generation format.

To generate the Intel® FPGA Temperature Sensor IP core using the clear box generator, perform the following steps:

  1. Create a text file (.txt) that contains your clear box ports and parameter settings in your working directory.

    For example, 
c:\altera\10.0\quartus\work\sample_param_test.txt.

    This figure shows a sample text file to generate the Intel® FPGA Temperature Sensor IP core.

    Figure 4. Sample Text File for Clear Box Generator
    Note: Ensure that you enclose String-type values with double-quotes.
  2. Access the command prompt of your operating system, and change the current directory to your working directory by typing the following command:

    cd c:\altera\10.0\quartus\work\

    The clear box executable file name is clearbox.exe.

    Note: When you install the Intel® Quartus® Prime software, the %QUARTUS_ROOTDIR%\bin is added into your system’s environment variables. Therefore, you can run the clear box command from any directory.
  3. To view the available ports and parameters for this IP core, type the following command at the command prompt of your operating system:

    clearbox alttemp_sense -h

  4. To generate the Intel® FPGA Temperature Sensor IP core variation file based on the ports and parameter settings in the text file, type the following command:

    clearbox alttemp_sense -f *.txt

    For example, clearbox alttemp_sense -f sample_param_test.txt

  5. After the clear box generator generates the IP core variation files, you can instantiate the IP core module in a HDL file or a block diagram file in the Intel® Quartus® Prime software.
  6. To view the estimated hardware resources that the Intel® FPGA Temperature Sensor IP core uses, type the following command:

    clearbox alttemp_sense -f sample_param_test.txt -resc_count

    Note: This command does not generate a HDL file.
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