Temperature Sensing Operation for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Figure 1. Intel® FPGA Temperature Sensor IP Core Top-Level Diagram for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
The following lists the features for Intel® FPGA Temperature Sensor IP core for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices:
- For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, the Intel® FPGA Temperature Sensor IP core supports the instantiation of temperature sensor block in your design from the IP Catalog.
- The Intel® Arria® 10 and Intel® Cyclone® 10 GX temperature sensor block runs at 1 MHz, where the clock signal is coming from the internal oscillator that is located in the temperature sensor block. Within the block, 10-bit ADC circuitry is included for converting sensor’s reading to digital output.
- The corectl signal is used as an enable signal. When asserting the corectl signal, the ADC starts the conversion and 10-bit data is available at tempout after 1,024 clock cycles. The corectl signal must remain asserted until the completion of 1,024 clock cycles. The eoc signal goes high for one clock cycle of the 1-MHz internal oscillator clock, indicating end of conversion. You can latch the data on tempout at the falling edge of eoc. When the corectl signal is left asserted, the ADC starts another conversion cycle and provides a new temperature value at tempout. However, if the corectl signal is de-asserted, tempout maintains its current temperature value until the corectl signal re-asserts, or the reset signal is asserted.
- You can reset the temperature sensor anytime by asserting the reset signal.