Intel® FPGA Temperature Sensor IP Core User Guide

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ID 683585
Date 5/30/2018
Public
Document Table of Contents
Document Table of Contents x
Intel® FPGA Temperature Sensor IP Core User Guide
Intel® FPGA Temperature Sensor IP Core User Guide x
Intel® FPGA Temperature Sensor Features Intel® FPGA Temperature Sensor Functional Description Using Clear Box Generator Intel® FPGA Temperature Sensor Device Support Intel® FPGA Temperature Sensor Parameters Transfer Function for Internal TSD Intel® FPGA Temperature Sensor IP Core Signals Intel® FPGA Temperature Sensor Prototypes and Component Declarations Document Revision History
Intel® FPGA Temperature Sensor Functional Description x
Temperature Sensing Operation for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices Temperature Sensing Operation for Arria® V, Arria® V GZ, Stratix® V, and Stratix® IV Devices
Temperature Sensing Operation for Arria® V, Arria® V GZ, Stratix® V, and Stratix® IV Devices x
Generating the Intel® FPGA Temperature Sensor IP Core Example Design Compiling the Intel® FPGA Temperature Sensor IP Core Example Design
Intel® FPGA Temperature Sensor Prototypes and Component Declarations x
Verilog HDL Prototype VHDL Component Declaration
Intel® FPGA Temperature Sensor IP Core User Guide

Generating the Intel® FPGA Temperature Sensor IP Core Example Design

To generate the Intel® FPGA Temperature Sensor IP core, download the example design and follow these steps:
  1. Open the alttemp_sense_ex1.zip file and extract alttemp_sense_ex1.qar.
  2. In the Intel® Quartus® Prime software, open the alttemp_sense_ex1.qar file and restore the archive file into your working directory.
  3. On the IP Catalog window, search and click Intel® FPGA Temperature Sensor .
  4. In the New IP Instance dialog box, type tsd_s4 as your top-level file name.
  5. In the Device family field, select Stratix® IV.
  6. Then, select your FPGA device family from the Device Family pull-down list. Click OK.
  7. In the Parameter Editor, set the following parameter settings.
    Table 2.  Configuration Settings for the Intel® FPGA Temperature Sensor IP Core
    Option Value
    What is the input frequency? 40 MHz
    What is the clock divider value? 80 MHz
    Create a clock enable port Turned on
    Create an asynchronous clear port Turned on
  8. Click Finish. The tsd_s4 module is built.
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