Intel® FPGA Temperature Sensor IP Core User Guide

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ID 683585
Date 5/30/2018
Public
Document Table of Contents
Document Table of Contents x
Intel® FPGA Temperature Sensor IP Core User Guide
Intel® FPGA Temperature Sensor IP Core User Guide x
Intel® FPGA Temperature Sensor Features Intel® FPGA Temperature Sensor Functional Description Using Clear Box Generator Intel® FPGA Temperature Sensor Device Support Intel® FPGA Temperature Sensor Parameters Transfer Function for Internal TSD Intel® FPGA Temperature Sensor IP Core Signals Intel® FPGA Temperature Sensor Prototypes and Component Declarations Document Revision History
Intel® FPGA Temperature Sensor Functional Description x
Temperature Sensing Operation for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices Temperature Sensing Operation for Arria® V, Arria® V GZ, Stratix® V, and Stratix® IV Devices
Temperature Sensing Operation for Arria® V, Arria® V GZ, Stratix® V, and Stratix® IV Devices x
Generating the Intel® FPGA Temperature Sensor IP Core Example Design Compiling the Intel® FPGA Temperature Sensor IP Core Example Design
Intel® FPGA Temperature Sensor Prototypes and Component Declarations x
Verilog HDL Prototype VHDL Component Declaration
Intel® FPGA Temperature Sensor IP Core User Guide

Document Revision History

This table lists the changes made to the document.
Document Version Intel® Quartus® Prime Version Changes
2018.05.30 17.1 Updated the description of the reset signal in the Intel® FPGA Temperature Sensor IP Core Signals for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices table.
Date Document Version Changes Made
September 2017 2017.09.14
  • Beginning from the Intel® Quartus® Prime software version 17.1, the name of this IP core has been changed from Altera Temperature Sensor IP Core to Intel® FPGA Temperature Sensor IP Core.
  • Added Intel® Cyclone® 10 GX devices information.
  • Changed instances of Quartus II to Intel® Quartus® Prime.
  • Added the link to Intel® FPGA Temperature Sensor IP core example design.
  • Added the Transfer Function for Internal TSD section.
  • Updated the Intel® FPGA Temperature Sensor IP Core Top-Level Diagram for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices figure.
  • Updated the Temperature Sensing Operation for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices section.
  • Updated the eoc description in the Intel® FPGA Temperature Sensor IP Core Signals for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices table.
May 2017 2017.05.08 Rebranded as Intel.
May 2015 2015.05.04
  • Added a link on how to calculate the temperature from the tempout[9:0] value.
  • Editorial updates.
December 2014 2014.12.15
  • Added Arria 10, Arria V, and Arria V GZ devices to the Device Support section.
  • Editorial changes to the warning message in Temperature Sensing Operation section.
  • Added Arria 10 devices information.
  • Updated template.
June 2013 3.1
  • Updated the “Temperature Sensing Operation” on page 3–1 to clarify that enabling the ADC allows you to measure the temperature of the device only once and to include a warning about a minimum pulse violation when input clock derived from a PLL.
  • Updated “Features” on page 1–1 to notify that this IP core does not provide simulation feature.
September 2010 3.0
  • Updated the Parameter Settings chapter.
  • Added the Prototypes and Component Declarations section.
  • Added the Clear Box Generator chapter.
February 2010 2.0 Updated the Temperature Sensing Operation section.
November 2009 1.0 Initial release.
Level Two Title