Visible to Intel only — GUID: eis1412132391134
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Intel® FPGA Temperature Sensor Features
Intel® FPGA Temperature Sensor Functional Description
Using Clear Box Generator
Intel® FPGA Temperature Sensor Device Support
Intel® FPGA Temperature Sensor Parameters
Transfer Function for Internal TSD
Intel® FPGA Temperature Sensor IP Core Signals
Intel® FPGA Temperature Sensor Prototypes and Component Declarations
Document Revision History
Visible to Intel only — GUID: eis1412132391134
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Compiling the Intel® FPGA Temperature Sensor IP Core Example Design
To compile the Intel® FPGA Temperature Sensor IP core in the Intel® Quartus® Prime software, follow these steps:
- Open the top-level file alttemp_sense_ex1.bdf in the Intel® Quartus® Prime Block Editor software. This file contains the input and output assignments and a placeholder for the tsd_s4 module.
- To insert the tsd_s4 module, double-click on the Block Editor window. The Symbol window appears.
- Under Name, browse to the tsd_s4.bsf file.
- Click OK.
- Place the tsd_s4 module onto the INSERT TSD_S4 BLOCK HERE placeholder so that the module aligns with the input and output ports.
Figure 3. Complete Design FileThis figure shows the complete design file.
- On the Processing menu, click Start Compilation.
- When the Full Compilation was successful message box appears, click OK.