Intel® FPGA Temperature Sensor IP Core User Guide

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ID 683585
Date 5/30/2018
Public
Document Table of Contents
Document Table of Contents x
Intel® FPGA Temperature Sensor IP Core User Guide
Intel® FPGA Temperature Sensor IP Core User Guide x
Intel® FPGA Temperature Sensor Features Intel® FPGA Temperature Sensor Functional Description Using Clear Box Generator Intel® FPGA Temperature Sensor Device Support Intel® FPGA Temperature Sensor Parameters Transfer Function for Internal TSD Intel® FPGA Temperature Sensor IP Core Signals Intel® FPGA Temperature Sensor Prototypes and Component Declarations Document Revision History
Intel® FPGA Temperature Sensor Functional Description x
Temperature Sensing Operation for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices Temperature Sensing Operation for Arria® V, Arria® V GZ, Stratix® V, and Stratix® IV Devices
Temperature Sensing Operation for Arria® V, Arria® V GZ, Stratix® V, and Stratix® IV Devices x
Generating the Intel® FPGA Temperature Sensor IP Core Example Design Compiling the Intel® FPGA Temperature Sensor IP Core Example Design
Intel® FPGA Temperature Sensor Prototypes and Component Declarations x
Verilog HDL Prototype VHDL Component Declaration
Intel® FPGA Temperature Sensor IP Core User Guide

Intel® FPGA Temperature Sensor Features

The following table lists the Intel® FPGA Temperature Sensor IP core features.
Table 1.   Intel® FPGA Temperature Sensor Features
Device Features
Stratix® V, Stratix IV, Arria® V, and Arria V GZ
  • An internal TSD with built-in 8-bit analog-to-digital converter (ADC) circuitry to monitor die temperature
  • A clock divider to reduce the frequency of the clock signal to 1 MHz or less before clocking the ADC
  • An asynchronous clear signal to reset the TSD block
Intel® Arria® 10 and Intel® Cyclone® 10 GX
  • An internal TSD with built-in 10-bit ADC circuitry clocked by 1 MHz internal oscillator to monitor die temperature
  • Does not require external clock source
  • An asynchronous clear signal to reset the TSD block
Note: The Intel® FPGA Temperature Sensor IP core does not have simulation model files and cannot be simulated.
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