Intel® FPGA Temperature Sensor IP Core User Guide

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ID 683585
Date 5/30/2018
Public
Document Table of Contents
Document Table of Contents x
Intel® FPGA Temperature Sensor IP Core User Guide
Intel® FPGA Temperature Sensor IP Core User Guide x
Intel® FPGA Temperature Sensor Features Intel® FPGA Temperature Sensor Functional Description Using Clear Box Generator Intel® FPGA Temperature Sensor Device Support Intel® FPGA Temperature Sensor Parameters Transfer Function for Internal TSD Intel® FPGA Temperature Sensor IP Core Signals Intel® FPGA Temperature Sensor Prototypes and Component Declarations Document Revision History
Intel® FPGA Temperature Sensor Functional Description x
Temperature Sensing Operation for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices Temperature Sensing Operation for Arria® V, Arria® V GZ, Stratix® V, and Stratix® IV Devices
Temperature Sensing Operation for Arria® V, Arria® V GZ, Stratix® V, and Stratix® IV Devices x
Generating the Intel® FPGA Temperature Sensor IP Core Example Design Compiling the Intel® FPGA Temperature Sensor IP Core Example Design
Intel® FPGA Temperature Sensor Prototypes and Component Declarations x
Verilog HDL Prototype VHDL Component Declaration
Intel® FPGA Temperature Sensor IP Core User Guide

Intel® FPGA Temperature Sensor Parameters

The parameters are applicable for all supported devices except Intel® Arria® 10 and Intel® Cyclone® 10 GX devices. There are no available parameters for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.

You can parameterize the Intel® FPGA Temperature Sensor IP core using the IP Catalog and parameter editor, or with the command-line interface (CLI). Use the parameter editor to quickly specify parameters in a GUI.

Expert users may choose to instantiate and parameterize the IP core through the command-line interface using the clear box generator command. This method requires you to have command-line scripting knowledge.

This table lists the parameter editor and CLI parameter settings for the Intel® FPGA Temperature Sensor IP core.

Table 3.   Intel® FPGA Temperature Sensor IP Core Parameter Settings
Parameter CLI Parameter Description
Name Legal Values Name Legal Values
General Options Tab
What is the input frequency? 1.0 – 80.0 MHz clk_frequency 1.0 – 80.0 Specifies the input frequency of the clk signal. The input frequency value is type string, and the value must be less than or equal to the clock divider value.

The default value is 1.0

What is the clock divider value? 40, 80 clock_divider_value 40, 80 Specifies the clock divider value. The IP core divides the clock frequency value with the clock divider value before feeding the ADC. This option is only enabled when the clk signal frequency is more than 1 MHz.

Intel recommends clocking the ADC with a 500 kHz signal.

The CLI parameter is type integer. Ensure that you enable the clock divider by setting the clock_divider_enable parameter value to on.

The default value is 40.

Create a clock enable port On/Off ce — Specifies whether to turn on the asynchronous clock enable (ce) port.

Turn on this option when you want to enable the Intel® FPGA Temperature Sensor IP core.

When you turn off this option, the clock enable port automatically connects to VCC.

Create an asynchronous clear port On/Off clr — Specifies whether to turn on the asynchronous clear (clr) port.

Turn on this option when you want to reset the Intel® FPGA Temperature Sensor IP core.

When you turn off this option, the clear port automatically connects to GND.

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