Temperature Sensing Operation for Arria® V, Arria® V GZ, Stratix® V, and Stratix® IV Devices
Figure 2. Intel® FPGA Temperature Sensor Block Diagram for Arria® V, Arria® V GZ, Stratix® V, and Stratix® IV DevicesThis figure shows the top-level ports and the basic building blocks of the Intel® FPGA Temperature Sensor IP core.
The Intel® FPGA Temperature Sensor IP core runs at the frequency of the clk signal. The clk signal can run at a frequency of 80 MHz and below. The clock divider divides the clk signal to 1 MHz or less to feed the ADC. You can set the value of the clock divider using the Intel® FPGA Temperature Sensor IP core parameter editor.
The ce signal connects to the output enable (oe) port of the clock divider block. Assert the ce signal to enable the Intel® FPGA Temperature Sensor IP core. When you deassert the ce signal, the IP core disables the ADC, and maintains the previous values of the tsdcalo[7..0] and tsdcaldone signals unless you assert the clr signal, or reset the device. The clr signal is asynchronous, and you must assert the clr signal at least one clock cycle of the adcclk signal to clear the output ports.
Enabling the ADC allows you to measure the device temperature only once. To perform another temperature measurement, assert the clr signal, or reset the device. The clr signal is asynchronous, and you must assert the clr signal at least one clock cycle of the ADC clk signal to clear the output ports.
Note: When you choose not to create the ce port, the IP core connects the ce port to VCC. In this case, the ADC circuitry is always enabled. Intel recommends that you disable the ADC by deasserting the ce signal when the ADC is not in use to reduce power consumption.
During device power-up or when you assert the asynchronous clr signal, the Intel® FPGA Temperature Sensor IP core sets the tsdcaldone port to 0 and the tsdcalo[7:0] signal to 11010101 or 0xD5. After 10 clock cycles of the adcclk signal, the Intel® FPGA Temperature Sensor IP core asserts the tsdcaldone signal to indicate that the temperature sensing operation is complete and that the value of the tsdcalo[7:0] signal is valid. The value of the tsdcalo[7:0] signal corresponds to the device temperature range. For more information about the value of tsdcalo[7:0] signals, refer to the Related Information. To start another temperature sensing operation, assert the clr signal for at least one clock cycle of the adcclk signal, or reset the device.
Note: When you choose not to create the clr port , the Intel® FPGA Temperature Sensor IP core connects the clr port to GND. In this case, you must reset the device to clear the output signals or start a temperature sensing operation. Intel recommends that you generate the clr port if you are planning to run the temperature sensing operation more than once.
If a derived PLL output clock is used to drive the Intel® FPGA Temperature Sensor IP core, a minimum pulse violation might occur. When using the Intel® FPGA Temperature Sensor IP core, you must ensure the clock applied must be less than or equal to 1 MHz. If you are using a higher frequency clock, the Intel® FPGA Temperature Sensor IP core allows you use the 40 or 80 clock divider to reduce the clock frequency to be less than or equal to 1.0MHz.