Intel Agilex® 7 F-Series and I-Series Known Issue List

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ID 683584
Date 5/03/2023
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Known Issue List for Intel Agilex® 7 Devices 3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata 4. Intel Agilex® 7 F-Series and I-Series User Guidelines 5. Document Revision History for the Intel Agilex® 7 F-Series and I-Series Known Issue List
2. Known Issue List for Intel Agilex® 7 Devices x
2.1. FPGA 2.2. Hard Processor System
2.1. FPGA x
2.1.1. Configuration and Security
2.1.1. Configuration and Security x
2.1.1.1. FPGA Reconfiguration May Cause Device to Halt 2.1.1.2. Secure Device Manager May Disable Physically Unclonable Function
2.2. Hard Processor System x
2.2.1. Write Data Can Appear at an AXI Interface before the Write Address, which can Cause a Deadlock Condition
3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata x
3.1. 843819: Memory Locations May be Accessed Speculatively Due to Instruction Fetches When HCR.VM is Set 3.2. 845719: A Load May Read Incorrect Data 3.3. 855871: ETM Does Not Report IDLE State When Disabled Using OSLOCK 3.4. 855872: A Store-Exclusive Instruction May Pass When it Should Fail 3.5. 711668: Configuration Extension Register Has Wrong Value Status 3.6. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow 3.7. 855873: An Eviction Might Overtake a Cache Clean Operation 3.8. 853172: ETM May Assert AFREADY Before All Data Has Been Output 3.9. 836870: Non-Allocating Reads May Prevent a Store Exclusive From Passing 3.10. 836919: Write of the JMCR in EL0 Does Not Generate an UNDEFINED Exception 3.11. 845819: Instruction Sequences Containing AES Instructions May Produce Incorrect Results 3.12. 851672: ETM May Trace an Incorrect Exception Address 3.13. 851871: ETM May Lose Counter Events While Entering WFx Mode 3.14. 852071: Direct Branch Instructions Executed Before a Trace Flush May be Output in an Atom Packet After Flush Acknowledgment 3.15. 852521: A64 Unconditional Branch May Jump to Incorrect Address 3.16. 855827: PMU Counter Values May Be Inaccurate When Monitoring Certain Events 3.17. 855829: Reads of PMEVCNTR<n> are not Masked by HDCR.HPMN 3.18. 855830: Loads of Mismatched Size May not be Single-Copy Atomic
1. About this Document
2. Known Issue List for Intel Agilex® 7 Devices
3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata
4. Intel Agilex® 7 F-Series and I-Series User Guidelines
5. Document Revision History for the Intel Agilex® 7 F-Series and I-Series Known Issue List

3.13. 851871: ETM May Lose Counter Events While Entering WFx Mode

Description

If the ETM resources become inactive because of a low-power state, there is a one-cycle window during which the counters and the sequencer may ignore counter-at-zero resources.

The following sequence is required for this erratum to occur:

  1. The core executes a WFI or WFE instruction.
  2. The ETM enters a low-power state.
  3. In a one-cycle window around this point, either:
    1. A counter in self-reload mode generates a counter-at-zero resource.
    2. A counter in normal mode gets a RLDEVENT on the cycle in which it has just transitioned to zero.
  4. A counter or sequencer is sensitive to the counter-at-zero resource.

Impact

Counters sensitive to a counter-at-zero resource may not reload or decrement. If the sequencer is sensitive to a counter-at-zero resource, it may not change state, or may change to an incorrect state.

Workaround

The ETM can be prevented from entering low-power mode by setting the LPOVERRIDE bit of Trace Event Control 1 (TRCEVENTCTL1R) register. This workaround is only needed if there is a counter or sequencer sensitive to a counter-at-zero resource.

Category

Category 3
Level Two Title