Arria 10 GX Transceiver Signal Integrity Development Kit User Guide

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ID 683553
Date 8/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. About This Development Kit 2. Getting Started 3. Development Board Setup 4. Board Update Portal 5. Board Components 6. Board Test System 7. Additional Information A. Programming the Flash Memory Device
1. About This Development Kit x
1.1. Development Kit Features 1.2. Handling the Board
1.1. Development Kit Features x
1.1.1. Hardware 1.1.2. Software 1.1.3. Development Kit Package
2. Getting Started x
2.1. Before You Begin 2.2. Activating your Software License 2.3. Inspect the Board 2.4. Installing the Development Kit 2.5. Installing the USB-Blaster Driver
3. Development Board Setup x
3.1. Setting Up the Board 3.2. Factory Default Switch Settings
4. Board Update Portal x
4.1. Connecting to the Board Update Portal Web Page 4.2. Using the Board Update Portal to Update User Designs
5. Board Components x
5.1. Board Overview 5.2. Arria 10 FPGA 5.3. MAX V CPLD 5.4. Configuration Elements 5.5. Status Elements 5.6. Setup Elements 5.7. Clock Circuits 5.8. General User Input/Output 5.9. Transceiver Channels 5.10. Communication Ports 5.11. Flash Memory 5.12. Power Supply
5.2. Arria 10 FPGA x
5.2.1. I/O Resources
5.4. Configuration Elements x
5.4.1. FPGA Programming over Embedded USB-Blaster 5.4.2. FPGA Programming from Flash Memory 5.4.3. FPGA Programming over External USB-Blaster
5.7. Clock Circuits x
5.7.1. Transceiver Dedicated Clocks 5.7.2. General Purpose Clocks 5.7.3. Embedded USB Blaster Clock
5.8. General User Input/Output x
5.8.1. User-Defined Push Buttons 5.8.2. User-Defined DIP Switch 5.8.3. User-Defined LEDs 5.8.4. Character LCD
5.12. Power Supply x
5.12.1. Power Measurement 5.12.2. Power Distribution System 5.12.3. Temperature Sense
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Version Selector 6.4. Using the Board Test System
6.4. Using the Board Test System x
6.4.1. The Configure Menu 6.4.2. The System Info Tab 6.4.3. The GPIO Tab 6.4.4. The Flash Tab 6.4.5. The XCVR #1 Tab 6.4.6. The XCVR #2 Tab 6.4.7. The XCVR #3 Tab 6.4.8. Power Monitoring 6.4.9. The Clock Control
6.4.2. The System Info Tab x
6.4.2.1. Board Information 6.4.2.2. MAX V Registers 6.4.2.3. JTAG Chain 6.4.2.4. Qsys Memory Map
6.4.3. The GPIO Tab x
6.4.3.1. Character LCD 6.4.3.2. User DIP Switches 6.4.3.3. User LEDs 6.4.3.4. Push Button Switches
6.4.4. The Flash Tab x
6.4.4.1. Read 6.4.4.2. Write 6.4.4.3. Random Test 6.4.4.4. CFI Info 6.4.4.5. Inc Test 6.4.4.6. Reset 6.4.4.7. Erase 6.4.4.8. Flash Memory Map
6.4.5. The XCVR #1 Tab x
6.4.5.1. Status 6.4.5.2. Port 6.4.5.3. PMA Setting 6.4.5.4. Data Type 6.4.5.5. Error Control 6.4.5.6. Run Control
6.4.6. The XCVR #2 Tab x
6.4.6.1. Status 6.4.6.2. Port 6.4.6.3. PMA Setting 6.4.6.4. Data Type 6.4.6.5. Error Control 6.4.6.6. Run Control
6.4.7. The XCVR #3 Tab x
6.4.7.1. Status 6.4.7.2. Port 6.4.7.3. PMA Setting 6.4.7.4. Data Type 6.4.7.5. Error Control 6.4.7.6. Run Control
6.4.9. The Clock Control x
6.4.9.1. Serial Port Registers 6.4.9.2. fXTAL 6.4.9.3. Target Frequency 6.4.9.4. Reset Si570 6.4.9.5. Set New Frequency
7. Additional Information x
7.1. User Guide Revision History
A. Programming the Flash Memory Device x
A.1. CFI Flash Memory Map A.2. Preparing Design Files for Flash Programming A.3. Creating Flash Files Using the Nios II EDS A.4. Programming Flash Memory Using the Board Update Portal A.5. Programming Flash Memory Using the Nios II EDS A.6. Restoring the Flash Device to the Factory Settings A.7. Restoring the MAX V CPLD to the Factory Settings
1. About This Development Kit
2. Getting Started
3. Development Board Setup
4. Board Update Portal
5. Board Components
6. Board Test System
7. Additional Information
A. Programming the Flash Memory Device

5.7.1. Transceiver Dedicated Clocks

The figure below shows the dedicated transceiver clocking that will be implemented for the FPGA. This clocking scheme will allow 4 different protocols to be running simultaneously by the Intel® Arria® 10 GX FPGA.

Four differential clock sources are provided from an I2C programmable VCO oscillator to the dedicated REFCLK input pins of transceiver blocks on both sides of the FPGA. The default frequencies for these four oscillators at startup are:-
  • 644.53125 MHz (Y3 left side xcvrs)
  • 706.25 MHz (Y4 left side xcvrs)
  • 625 MHz (Y5 right side xcvrs)
  • 875 MHz (Y6 right side xcvrs)

The default frequencies can be overridden and a different frequency can be programmed into the oscillators for support of other protocols.

CAUTION:
Programmed frequencies will be lost upon a board power down condition. Oscillator frequencies return to their default frequency upon power up.

Each oscillator will support a programmable frequency range of 10 MHz - 1.4 GHz and provide a differential LVDS trigger output to SMA connectors for scope or other lab equipment triggering purposes.

In addition to the four oscillators, each side will have a dedicated differential REFCLK input from a pair of SMA connectors to allow use of lab equipment clock generators as the transceiver clock source.

The clock inputs described above all pass through a clock buffer first, the two inputs below connect directly to the transceiver clock inputs:-
  • J122/J123 SMA connectors direct connection to REFCLK_GXBL1F block.
  • J124/J125 SMA connectors direct connection to REFCLK_GXBR4F block.
Figure 9. Transceiver Dedicated Clocking
Level Two Title