Arria 10 GX Transceiver Signal Integrity Development Kit User Guide

Download PDF
ID 683553
Date 8/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. About This Development Kit 2. Getting Started 3. Development Board Setup 4. Board Update Portal 5. Board Components 6. Board Test System 7. Additional Information A. Programming the Flash Memory Device
1. About This Development Kit x
1.1. Development Kit Features 1.2. Handling the Board
1.1. Development Kit Features x
1.1.1. Hardware 1.1.2. Software 1.1.3. Development Kit Package
2. Getting Started x
2.1. Before You Begin 2.2. Activating your Software License 2.3. Inspect the Board 2.4. Installing the Development Kit 2.5. Installing the USB-Blaster Driver
3. Development Board Setup x
3.1. Setting Up the Board 3.2. Factory Default Switch Settings
4. Board Update Portal x
4.1. Connecting to the Board Update Portal Web Page 4.2. Using the Board Update Portal to Update User Designs
5. Board Components x
5.1. Board Overview 5.2. Arria 10 FPGA 5.3. MAX V CPLD 5.4. Configuration Elements 5.5. Status Elements 5.6. Setup Elements 5.7. Clock Circuits 5.8. General User Input/Output 5.9. Transceiver Channels 5.10. Communication Ports 5.11. Flash Memory 5.12. Power Supply
5.2. Arria 10 FPGA x
5.2.1. I/O Resources
5.4. Configuration Elements x
5.4.1. FPGA Programming over Embedded USB-Blaster 5.4.2. FPGA Programming from Flash Memory 5.4.3. FPGA Programming over External USB-Blaster
5.7. Clock Circuits x
5.7.1. Transceiver Dedicated Clocks 5.7.2. General Purpose Clocks 5.7.3. Embedded USB Blaster Clock
5.8. General User Input/Output x
5.8.1. User-Defined Push Buttons 5.8.2. User-Defined DIP Switch 5.8.3. User-Defined LEDs 5.8.4. Character LCD
5.12. Power Supply x
5.12.1. Power Measurement 5.12.2. Power Distribution System 5.12.3. Temperature Sense
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Version Selector 6.4. Using the Board Test System
6.4. Using the Board Test System x
6.4.1. The Configure Menu 6.4.2. The System Info Tab 6.4.3. The GPIO Tab 6.4.4. The Flash Tab 6.4.5. The XCVR #1 Tab 6.4.6. The XCVR #2 Tab 6.4.7. The XCVR #3 Tab 6.4.8. Power Monitoring 6.4.9. The Clock Control
6.4.2. The System Info Tab x
6.4.2.1. Board Information 6.4.2.2. MAX V Registers 6.4.2.3. JTAG Chain 6.4.2.4. Qsys Memory Map
6.4.3. The GPIO Tab x
6.4.3.1. Character LCD 6.4.3.2. User DIP Switches 6.4.3.3. User LEDs 6.4.3.4. Push Button Switches
6.4.4. The Flash Tab x
6.4.4.1. Read 6.4.4.2. Write 6.4.4.3. Random Test 6.4.4.4. CFI Info 6.4.4.5. Inc Test 6.4.4.6. Reset 6.4.4.7. Erase 6.4.4.8. Flash Memory Map
6.4.5. The XCVR #1 Tab x
6.4.5.1. Status 6.4.5.2. Port 6.4.5.3. PMA Setting 6.4.5.4. Data Type 6.4.5.5. Error Control 6.4.5.6. Run Control
6.4.6. The XCVR #2 Tab x
6.4.6.1. Status 6.4.6.2. Port 6.4.6.3. PMA Setting 6.4.6.4. Data Type 6.4.6.5. Error Control 6.4.6.6. Run Control
6.4.7. The XCVR #3 Tab x
6.4.7.1. Status 6.4.7.2. Port 6.4.7.3. PMA Setting 6.4.7.4. Data Type 6.4.7.5. Error Control 6.4.7.6. Run Control
6.4.9. The Clock Control x
6.4.9.1. Serial Port Registers 6.4.9.2. fXTAL 6.4.9.3. Target Frequency 6.4.9.4. Reset Si570 6.4.9.5. Set New Frequency
7. Additional Information x
7.1. User Guide Revision History
A. Programming the Flash Memory Device x
A.1. CFI Flash Memory Map A.2. Preparing Design Files for Flash Programming A.3. Creating Flash Files Using the Nios II EDS A.4. Programming Flash Memory Using the Board Update Portal A.5. Programming Flash Memory Using the Nios II EDS A.6. Restoring the Flash Device to the Factory Settings A.7. Restoring the MAX V CPLD to the Factory Settings
1. About This Development Kit
2. Getting Started
3. Development Board Setup
4. Board Update Portal
5. Board Components
6. Board Test System
7. Additional Information
A. Programming the Flash Memory Device

5.2.1. I/O Resources

The table below summarizes the FPGA I/O usage by function on the Arria 10 GX transceiver signal integrity development board.
Table 5.  Arria 10 GX I/O Usage Summary
Function I/O Count Description
Configuration
JTAG USB Blaster or JTAG Header 4 Built-in USB-Blaster or JTAG 0.1-mm header for debugging
MSEL [2:0] 3 Configuration input pins to set configuration scheme
FPGA_CONF_DONE 1 Configuration done pin
FPGA_nSTATUS 1 Configuration status pin
FPGA_INIT_DONE 1 Configuration pin to signify user mode
FPGA_nCSO 1 Chip select pin to EPCQ device
FPGA_nCONFIG 1 Configuration input pin to reset FPGA
CLKUSR-100MHz 1 100 MHz Clock
FPGA_DCLK 1 Configuration Clock for PS and FPP configuration schemes
CPU_RESETn 1 Configuration input pin that clears all device registers
DEV_OE 1 Configuration input pin that enables all IOs
FPGA_CONFIG_D[31:0] 32 Configuration data input pins
FPGA_AS_DATA[3:0] 4 EPCQ data bus
PCIE_RESET 1 Reset pin for PCIe HIP
FPGA_PR_DONE 1 Partial reconfiguration done pin
FPGA_PR_REQUEST 1 Partial reconfiguration request pin
FPGA_PR_READY 1 Partial reconfiguration ready pin
FPGA_PR_ERROR 1 Partial reconfiguration error pin
USB
USB_FULL 1 USB FIFO is full
USB_EMPTY 1 USB FIFO is empty
USB_RESETn 1 USB Reset
USB_OEn 1 USB Output Enable
USB_RDn 1 USB Read
USB_WRn 1 USB Write
USB_DATA[7:0] 8 USB Data Bus
USB_ADDR[1:0] 2 USB Address Bus
USB_SCL 1 USB Serial Clock
USB_SDA 1 USB Serial Data
Flash Memory
F M_D[31:0] 32 Flash data bus
FM_A[26:1] 26 Flash address bus
FLASH_WEn 1 Flash write enable strobe
FLASH_CEn0 1 Flash chip enable
FLASH_CEn1 1 Flash chip enable
FLASH_OEn 1 Flash output enable
FLASH_RDYBSYn0 1 Flash ready or busy
FLASH_RDYBSYn1 1 Flash ready or busy
FLASH_RESETn 1 Flash reset
FLASH_CLK 1 Flash clock
FLASH_ADVn 1 Flash address valid
MAX V CPLD
MAX5_OEn 1 Output Enable
MAX5_CSn 1 Chip Select
MAX5_WEn 1 Write Enable
MAX5_CLK 1 Clock
MAX5_BEn[3:0] 4 Byte Enable
Switches, Buttons, LED
USER_LED [7:0] 8 Light Emitting Diode
USER_PB [7:0] 8 Push Buttons
USER_DIP [6:0] 7 DIP Switches
USER_IO [9:0] 10 Input/Output
A10_UNLOCK 1 FPGA Unlock Switch
Ethernet
ENET_SGMII_TX_P/N 2 Ethernet SGMII transmit data
ENET_SGMII_RX_P/N 2 Ethernet SGMII receive data
ENET_RSTn 1 Reset
ENET_INTn 1 Interrupt
MDIO 1 Ethernet Management Data IO
MDC 1 Ethernet Management Data Clock
Temperature Sense
Temperature Sense Diodes 2 Arria 10 internal sense diode
Transceivers
SFP_TX_DIS 1 SFP + TX disable control pin
SFP_RS0 1 SFP + Rate Select - Receiver Control Pin
SFP_RS1 1 SFP + Rate Select - Transmit Control Pin
SFP_MOD_ABS 1 SFP + Module Absent Status Pin
SFP_RX_LOS 1 SFP + Loss of Signal Status Pin
SFP_TX_FLT 1 SFP + Transmitter Fault Status Pin
CFP2_MOD_LOPWR 1 CFP2 Module Low Power Mode
CFP2_MOD_RSTn 1 CFP2 Module Reset
CFP2_PRG_CNTL[3:1] 3 CFP2 Program Control bits
CFP2_PRG_ALRM[3:1] 3 CFP2 Program Alarm bits
CFP2_PRG_PRTADR[2:0] 3 CFP2 MDIO Physical Port Address
CFP2_TX_DIS 1 CFP2 Transmitter Disable
CFP2_RX_LOS 1 CFP2 Receiver loss of signal
CFP2_MOD_ABS 1 CFP2 Module Absent
CFP2_MDC 1 CFP2 Management Data Clock
CFP2_MDIO 1 CFP2 Management Data I/O Bi-Directional Data
CFP2_GLB_ALRMn 1 CFP2 Global Alarm
Global Clocks
USB_FPGA_CLK 1 USB FPGA Clock
50MHz_A10GX_CLK 1 50 MHz Global clock input
50MHz_CLK3D 1 50 MHz Global clock input
A10GX_CLK2Jp 1 Global Clock input (selectable freq/ spread %)
A10GX_CLK2Jn 1 Global Clock input (selectable freq/ spread %)
A10GX_CLK3Bp 1 Global Clock input from SMA
A10GX_CLK3Bn 1 Global Clock input from SMA
100MHZ_LVDS_CLK3p 1 Differential global clock
100MHZ_LVDS_CLK3n 1 Differential global clock
100MHZ_LVDS_CLK2p 1 Differential global clock
100MHZ_LVDS_CLK2n 1 Differential global clock
100MHZ_LVDS_CLK1p 1 Differential global clock
100MHZ_LVDS_CLK1n 1 Differential global clock
CLK_125MHz_P/N 2 125 MHz differential core clock
Transceiver Clocks
REFCLK_GXBL_1E_T 2 Differential REFCLK input to the left side of xcvr block 1E
REFCLK_GXBL_1F_T 2 Differential REFCLK input to the left side of xcvr block 1F
REFCLK_GXBL_1G_T 2 Differential REFCLK input on the left side of xcvr block 1G
REFCLK_GXBL_1H_T 2 Differential REFCLK input to the left side of xcvr block 1H
REFCLK_GXBL_1D_T 2 Differential REFCLK input to the left side of xcvr block 1D
REFCLK_GXBL_1C_T 2 Differential REFCLK input to the left side of xcvr block 1C
REFCLK_GXBL_1E_T 2 Differential REFCLK input to the left side of xcvr block 1E
REFCLK_GXBL_1G_T 2 Differential REFCLK input to the left side of xcvr block 1G
REFCLK_GXBR_4E_T 2 Differential REFCLK input to the left side of xcvr block 4E
REFCLK_GXBR_4F_T 2 Differential REFCLK input to the left side of xcvr block 4F
REFCLK_GXBR_4G_T 2 Differential REFCLK input to the left side of xcvr block 4G
REFCLK_GXBR_4H_T 2 Differential REFCLK input to the left side of xcvr block 4H
REFCLK_GXBR_4C_T 2 Differential REFCLK input to the left side of xcvr block 4C
REFCLK_GXBR_4C_B 2 Differential REFCLK input to feed the channels on the right side of the Arria 10 GX device 4C
REFCLK_GXBR_4D_B 2 Differential REFCLK input to the left side of xcvr block 4D
REFCLK_GXBR_4E_B 2 Differential REFCLK input to the left side of xcvr block 4E
REFCLK_GXBR_4H_B 2 Differential REFCLK input to the left side of xcvr block 4H
Level Two Title