Arria 10 GX Transceiver Signal Integrity Development Kit User Guide

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ID 683553
Date 8/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. About This Development Kit 2. Getting Started 3. Development Board Setup 4. Board Update Portal 5. Board Components 6. Board Test System 7. Additional Information A. Programming the Flash Memory Device
1. About This Development Kit x
1.1. Development Kit Features 1.2. Handling the Board
1.1. Development Kit Features x
1.1.1. Hardware 1.1.2. Software 1.1.3. Development Kit Package
2. Getting Started x
2.1. Before You Begin 2.2. Activating your Software License 2.3. Inspect the Board 2.4. Installing the Development Kit 2.5. Installing the USB-Blaster Driver
3. Development Board Setup x
3.1. Setting Up the Board 3.2. Factory Default Switch Settings
4. Board Update Portal x
4.1. Connecting to the Board Update Portal Web Page 4.2. Using the Board Update Portal to Update User Designs
5. Board Components x
5.1. Board Overview 5.2. Arria 10 FPGA 5.3. MAX V CPLD 5.4. Configuration Elements 5.5. Status Elements 5.6. Setup Elements 5.7. Clock Circuits 5.8. General User Input/Output 5.9. Transceiver Channels 5.10. Communication Ports 5.11. Flash Memory 5.12. Power Supply
5.2. Arria 10 FPGA x
5.2.1. I/O Resources
5.4. Configuration Elements x
5.4.1. FPGA Programming over Embedded USB-Blaster 5.4.2. FPGA Programming from Flash Memory 5.4.3. FPGA Programming over External USB-Blaster
5.7. Clock Circuits x
5.7.1. Transceiver Dedicated Clocks 5.7.2. General Purpose Clocks 5.7.3. Embedded USB Blaster Clock
5.8. General User Input/Output x
5.8.1. User-Defined Push Buttons 5.8.2. User-Defined DIP Switch 5.8.3. User-Defined LEDs 5.8.4. Character LCD
5.12. Power Supply x
5.12.1. Power Measurement 5.12.2. Power Distribution System 5.12.3. Temperature Sense
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Version Selector 6.4. Using the Board Test System
6.4. Using the Board Test System x
6.4.1. The Configure Menu 6.4.2. The System Info Tab 6.4.3. The GPIO Tab 6.4.4. The Flash Tab 6.4.5. The XCVR #1 Tab 6.4.6. The XCVR #2 Tab 6.4.7. The XCVR #3 Tab 6.4.8. Power Monitoring 6.4.9. The Clock Control
6.4.2. The System Info Tab x
6.4.2.1. Board Information 6.4.2.2. MAX V Registers 6.4.2.3. JTAG Chain 6.4.2.4. Qsys Memory Map
6.4.3. The GPIO Tab x
6.4.3.1. Character LCD 6.4.3.2. User DIP Switches 6.4.3.3. User LEDs 6.4.3.4. Push Button Switches
6.4.4. The Flash Tab x
6.4.4.1. Read 6.4.4.2. Write 6.4.4.3. Random Test 6.4.4.4. CFI Info 6.4.4.5. Inc Test 6.4.4.6. Reset 6.4.4.7. Erase 6.4.4.8. Flash Memory Map
6.4.5. The XCVR #1 Tab x
6.4.5.1. Status 6.4.5.2. Port 6.4.5.3. PMA Setting 6.4.5.4. Data Type 6.4.5.5. Error Control 6.4.5.6. Run Control
6.4.6. The XCVR #2 Tab x
6.4.6.1. Status 6.4.6.2. Port 6.4.6.3. PMA Setting 6.4.6.4. Data Type 6.4.6.5. Error Control 6.4.6.6. Run Control
6.4.7. The XCVR #3 Tab x
6.4.7.1. Status 6.4.7.2. Port 6.4.7.3. PMA Setting 6.4.7.4. Data Type 6.4.7.5. Error Control 6.4.7.6. Run Control
6.4.9. The Clock Control x
6.4.9.1. Serial Port Registers 6.4.9.2. fXTAL 6.4.9.3. Target Frequency 6.4.9.4. Reset Si570 6.4.9.5. Set New Frequency
7. Additional Information x
7.1. User Guide Revision History
A. Programming the Flash Memory Device x
A.1. CFI Flash Memory Map A.2. Preparing Design Files for Flash Programming A.3. Creating Flash Files Using the Nios II EDS A.4. Programming Flash Memory Using the Board Update Portal A.5. Programming Flash Memory Using the Nios II EDS A.6. Restoring the Flash Device to the Factory Settings A.7. Restoring the MAX V CPLD to the Factory Settings
1. About This Development Kit
2. Getting Started
3. Development Board Setup
4. Board Update Portal
5. Board Components
6. Board Test System
7. Additional Information
A. Programming the Flash Memory Device

5.4.2. FPGA Programming from Flash Memory

The figure below shows the high-level conceptual block diagram for the MAX® V + Flash Fast Passive Parallel (FPP) configuration.
Figure 6. MAX V + Flash FPP x32 Configuration Conceptual Diagram
The figure below shows a more detailed schematic block diagram for the MAX® V + Flash FPP mode implementation.
Figure 7. Detailed MAX V + Flash FPP x32 Configuration Schematic

Once the FPGA is successfully initialized and in user mode, the CPLD will tri-state its Flash interface signals to avoid contention with the FPGA. A PGMSEL dipswitch (SW3) is provided to select between two POF files (FACTORY or USER) stored on the Flash. The Parallel Flash Loader (PFL) Megafunction will be used to implement FPP x32 configuration in the MAX® V CPLD. The PFL Megafunction reads data from the flash and converts it to Fast Passive Parallel format. This data is written to the Intel® Arria® 10 FPGA device dedicated DCLK and D[31:0] configuration pins at 50 MHz. The actual configuration data rate is limited by the flash read speed.

Implementation will be done using an Altera MAX® V 5M2210ZF256FBGA CPLD acting as the FPP download controller and two 1G Flash devices. The flash will be a Numonyx 1.8V core, 1.8V I/O 1Gigabit CFI NOR-type device (P/N: PC28F00AP30BF). The MAX® V CPLD will share the CFI Flash interface with the Intel® Arria® 10 GX FPGA. No arbitration is needed between the MAX® V CPLD and Intel® Arria® 10 GX FPGA to access the Flash as the CPLD only has access prior to FPGA initialization.

After a POWER-ON or RESET (re-configuration) event, the MAX® V device will configure the Arria 10 GX FPGA in FPP x32 mode with either the FACTORY POF or a USER defined POF depending on the FACTORY_LOAD setting. The PGMSEL bit is set via a pushbutton and observing the appropriate LED indicating a Factory or User file to be loaded. After selection of the program file; another pushbutton is press to load the program; that button is the PGM_CONFIG button.

The MSEL [2:0] pins indicate which passive mode is being used and whether the Fast or Slow POR delay is chosen. The data bus width information is contained in the Mode Select Decode Frame that is part of the configuration data. PORSEL is an internal signal decoded from MSEL[2:0] pins. PORSEL = 1 selects a Fast POR delay between 4-12ms. PORSEL = 0 selects a Slow POR delay between 100-300ms.The manufacturing default condition should be [000] for a Fast POR Delay mode without decompression or security enabled.

The 4 modes of Passive Programming are passive serial, passive parallel x8, passive parallel x16, and passive parallel x32.

For FPPx32 modes, MSEL [2:0] signals need to be set according to the table below
Table 7.  Supported FPPx32 Modes
MSEL[2:0] Mode of Operation Voltages Supported (v) POR Delay (ms)
000 Passive Fast 1.8 4-12
001 Passive Slow 1.8 100-300
010 Active Fast 1.8 4-12
011 Active Slow 1.8 100-300
100 ATPG 1.8 4-12
101 Test 1.8 4-12
110 Test Verify 1.8 4-12
111 Regscan 1.8 4-12
The LEDs associated with program load of FPPx32 mode configuration status as follows:
  • PGM_LED0 : ON when FACTORY image is selected
  • PGM_LED1 : ON when USER #1 image is selected
  • PGM_LED2 : ON when USER #2 image is selected
  • MAX_ERROR : ON when a Configuration Error has occurred
  • MAX_LOAD : ON when image is being loaded
  • MAX_CONF_DONE : ON when FPGA is successfully configured
Note: All the LEDs listed above are green.
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