Arria 10 GX Transceiver Signal Integrity Development Kit User Guide

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ID 683553
Date 8/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. About This Development Kit 2. Getting Started 3. Development Board Setup 4. Board Update Portal 5. Board Components 6. Board Test System 7. Additional Information A. Programming the Flash Memory Device
1. About This Development Kit x
1.1. Development Kit Features 1.2. Handling the Board
1.1. Development Kit Features x
1.1.1. Hardware 1.1.2. Software 1.1.3. Development Kit Package
2. Getting Started x
2.1. Before You Begin 2.2. Activating your Software License 2.3. Inspect the Board 2.4. Installing the Development Kit 2.5. Installing the USB-Blaster Driver
3. Development Board Setup x
3.1. Setting Up the Board 3.2. Factory Default Switch Settings
4. Board Update Portal x
4.1. Connecting to the Board Update Portal Web Page 4.2. Using the Board Update Portal to Update User Designs
5. Board Components x
5.1. Board Overview 5.2. Arria 10 FPGA 5.3. MAX V CPLD 5.4. Configuration Elements 5.5. Status Elements 5.6. Setup Elements 5.7. Clock Circuits 5.8. General User Input/Output 5.9. Transceiver Channels 5.10. Communication Ports 5.11. Flash Memory 5.12. Power Supply
5.2. Arria 10 FPGA x
5.2.1. I/O Resources
5.4. Configuration Elements x
5.4.1. FPGA Programming over Embedded USB-Blaster 5.4.2. FPGA Programming from Flash Memory 5.4.3. FPGA Programming over External USB-Blaster
5.7. Clock Circuits x
5.7.1. Transceiver Dedicated Clocks 5.7.2. General Purpose Clocks 5.7.3. Embedded USB Blaster Clock
5.8. General User Input/Output x
5.8.1. User-Defined Push Buttons 5.8.2. User-Defined DIP Switch 5.8.3. User-Defined LEDs 5.8.4. Character LCD
5.12. Power Supply x
5.12.1. Power Measurement 5.12.2. Power Distribution System 5.12.3. Temperature Sense
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Version Selector 6.4. Using the Board Test System
6.4. Using the Board Test System x
6.4.1. The Configure Menu 6.4.2. The System Info Tab 6.4.3. The GPIO Tab 6.4.4. The Flash Tab 6.4.5. The XCVR #1 Tab 6.4.6. The XCVR #2 Tab 6.4.7. The XCVR #3 Tab 6.4.8. Power Monitoring 6.4.9. The Clock Control
6.4.2. The System Info Tab x
6.4.2.1. Board Information 6.4.2.2. MAX V Registers 6.4.2.3. JTAG Chain 6.4.2.4. Qsys Memory Map
6.4.3. The GPIO Tab x
6.4.3.1. Character LCD 6.4.3.2. User DIP Switches 6.4.3.3. User LEDs 6.4.3.4. Push Button Switches
6.4.4. The Flash Tab x
6.4.4.1. Read 6.4.4.2. Write 6.4.4.3. Random Test 6.4.4.4. CFI Info 6.4.4.5. Inc Test 6.4.4.6. Reset 6.4.4.7. Erase 6.4.4.8. Flash Memory Map
6.4.5. The XCVR #1 Tab x
6.4.5.1. Status 6.4.5.2. Port 6.4.5.3. PMA Setting 6.4.5.4. Data Type 6.4.5.5. Error Control 6.4.5.6. Run Control
6.4.6. The XCVR #2 Tab x
6.4.6.1. Status 6.4.6.2. Port 6.4.6.3. PMA Setting 6.4.6.4. Data Type 6.4.6.5. Error Control 6.4.6.6. Run Control
6.4.7. The XCVR #3 Tab x
6.4.7.1. Status 6.4.7.2. Port 6.4.7.3. PMA Setting 6.4.7.4. Data Type 6.4.7.5. Error Control 6.4.7.6. Run Control
6.4.9. The Clock Control x
6.4.9.1. Serial Port Registers 6.4.9.2. fXTAL 6.4.9.3. Target Frequency 6.4.9.4. Reset Si570 6.4.9.5. Set New Frequency
7. Additional Information x
7.1. User Guide Revision History
A. Programming the Flash Memory Device x
A.1. CFI Flash Memory Map A.2. Preparing Design Files for Flash Programming A.3. Creating Flash Files Using the Nios II EDS A.4. Programming Flash Memory Using the Board Update Portal A.5. Programming Flash Memory Using the Nios II EDS A.6. Restoring the Flash Device to the Factory Settings A.7. Restoring the MAX V CPLD to the Factory Settings
1. About This Development Kit
2. Getting Started
3. Development Board Setup
4. Board Update Portal
5. Board Components
6. Board Test System
7. Additional Information
A. Programming the Flash Memory Device

5.9. Transceiver Channels

The Intel® Arria® 10 GX transceiver signal integrity development board dedicates 29 transceiver channels from both the left and right sides of the device. Transceiver channels are allocated as shown in the table below
Table 14.  Arria 10 Transceiver Channels
Transceiver Channel Data Rate Number of channels
High Density Connector - J46 (Samtec Bullseye connector) 15 Gbps 5
High Density Connector - J47 (Samtec Bullseye connector) 15 Gbps 5
Amphenol (Excede+) Backplane Connector 15 Gbps 4
CFP2 Optical Interface 25.78 Gbps (applies to GT device only) 4
SFP+ Optical Interface 14 Gbps 1
QSFP+ Optical Interface 25.78 Gbps (applies to GT device only) 4
2.4 mm SMA 'Gold' channel 15 Gbps 1
2.4 mm SMA 'Platinum' channel 15 Gbps 1
2.4 mm SMA channels 15 Gbps 4
Figure 11. Arria 10 GX Transceiver Usage Block Diagram
Table 15.  Amphenol Backplane Connector (J22)
Signal Net Name FPGA Pin Number Description
GXBR_4H_TX0p D1 GXB transmit
GXBR_4H_TX0n D2 GXB transmit
GXBR_4H_TX1p C3 GXB transmit
GXBR_4H_TX1n C4 GXB transmit
GXBR_4H_TX2p B1 GXB transmit
GXBR_4H_TX2n B2 GXB transmit
GXBR_4H_TX3p A3 GXB transmit
GXBR_4H_TX3n A4 GXB transmit
GXBR_4H_RX0p H5 GXB receive
GXBR_4H_RX0n H6 GXB receive
GXBR_4H_RX1p G7 GXB receive
GXBR_4H_RX1n G8 GXB receive
GXBR_4H_RX2p F5 GXB receive
GXBR_4H_RX2n F6 GXB receive
GXBR_4H_RX3p E7 GXB receive
GXBR_4H_RX3n E8 GXB receive
Table 16.  QSFP+ Connector Interface (J28)
Signal Net Name FPGA Pin Number Description
GXBL_1E_TX0p AP44 GXB transmit
GXBL_1E_TX0n AP43 GXB transmit
GXBL_1E_TX1p AM44 GXB transmit
GXBL_1E_TX1n AM43 GXB transmit
GXBL_1E_TX3p AH44 GXB transmit
GXBL_1E_TX3n AH43 GXB transmit
GXBL_1E_TX4p AF44 GXB transmit
GXBL_1E_TX4n AF43 GXB transmit
GXBL_1E_RX0p AG42 GXB receive
GXBL_1E_RX0n AG41 GXB receive
GXBL_1E_RX1p AF40 GXB receive
GXBL_1E_RX1n AF39 GXB receive
GXBL_1E_RX3p AD40 GXB receive
GXBL_1E_RX3n AD39 GXB receive
GXBL_1E_RX4p AC42 GXB receive
GXBL_1E_RX4n AC41 GXB receive
Table 17.  SFP+ Interface Connector (J29)
Signal Net Name FPGA Pin Number Description
GXBR_4C_TX0p BC7 GXB transmit
GXBR_4C_TX0n BC8 GXB transmit
GXBR_4C_RX0p AW7 GXB receive
GXBR_4C_RX0n AW8 GXB receive
Table 18.  CFP2 Interface Connector (J24A / J24B)
Signal Net Name FPGA Pin Number Description
GXBL_1H_TX0p D44 GXB transmit
GXBL_1H_TX0n D43 GXB transmit
GXBL_1H_TX1p C42
GXB transmit
Note: TX1 p/n pins swapped at CFP2 connector J24B
GXBL_1H_TX1n C41
GXB transmit
Note: TX1 p/n pins swapped at CFP2 connector J24B
GXBL_1H_TX3p A42 GXB transmit
GXBL_1H_TX3n A41 GXB transmit
GXBL_1H_TX4p B40
GXB transmit
Note: TX4 p/n pins swapped at CFP2 connector J24B
GXBL_1H_TX4n B39
GXB transmit
Note: TX4 p/n pins swapped at CFP2 connector J24B
GXBL_1H_RX0p H40
GXB receive
Note: RX0 p/n pins swapped at CFP2 connector J24B
GXBL_1H_RX0n H39
GXB receive
Note: RX0 p/n pins swapped at CFP2 connector J24B
GXBL_1H_RX1p G38 GXB receive
GXBL_1H_RX1n G37 GXB receive
GXBL_1H_RX3p E37
GXB receive
Note: RX3 p/n pins swapped at FPGA
GXBL_1H_RX3n E38
GXB receive
Note: RX3 p/n pins swapped at FPGA
GXBL_1H_RX4p D40 GXB receive
GXBL_1H_RX4n D39 GXB receive
Table 19.  High Density Connectors - 2.4mm SMA Connectors (J46 / J47)
Signal Net Name FPGA Pin Number Description
GXBR_4E_TX_2p AK1 GXB transmit
GXBR_4E_TX_2n AK2 GXB transmit
GXBR_4E_TX_3p AH1 GXB transmit
GXBR_4E_TX_3n AH2 GXB transmit
GXBR_4E_TX_4p AF1 GXB transmit
GXBR_4E_TX_4n AF2 GXB transmit
GXBR_4E_TX_5p AD1 GXB transmit
GXBR_4E_TX_5n AD2 GXB transmit
GXBR_4E_RX_2p AE3 GXB receive
GXBR_4E_RX_2n AE4 GXB receive
GXBR_4E_RX_3p AD5 GXB receive
GXBR_4E_RX_3n AD6 GXB receive
GXBR_4E_RX_4p AC3 GXB receive
GXBR_4E_RX_4n AC4 GXB receive
GXBR_4E_RX_5p AB5 GXB receive
GXBR_4E_RX_5n AB6 GXB receive
GXBR_4F_TX_0p AB1 GXB transmit
GXBR_4F_TX_0n AB2 GXB transmit
GXBR_4F_TX_1p Y1 GXB transmit
GXBR_4F_TX_1n Y2 GXB transmit
GXBR_4F_TX_2p V1 GXB transmit
GXBR_4F_TX_2n V2 GXB transmit
GXBR_4F_TX_3p T1 GXB transmit
GXBR_4F_TX_3n T2 GXB transmit
GXBR_4F_TX_4p P1 GXB transmit
GXBR_4F_TX_4n P2 GXB transmit
GXBR_4F_TX_5p M1 GXB transmit
GXBR_4F_TX_5n M2 GXB transmit
GXBR_4F_RX_0p AA3 GXB receive
GXBR_4F_RX_0n AA4 GXB receive
GXBR_4F_RX_1p W3 GXB receive
GXBR_4F_RX_1n W4 GXB receive
GXBR_4F_RX_2p Y5 GXB receive
GXBR_4F_RX_2n Y6 GXB receive
GXBR_4F_RX_3p V5 GXB receive
GXBR_4F_RX_3n V6 GXB receive
GXBR_4F_RX_4p U3 GXB receive
GXBR_4F_RX_4n U4 GXB receive
GXBR_4F_RX_5p T5 GXB receive
GXBR_4F_RX_5n T6 GXB receive
Level Two Title