R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 7/08/2024
Public
Document Table of Contents

2.7.4. Running the Performance Design Example for TL Bypass Mode

To run the Performance Design Example for TL Bypass mode, repeat steps 1 to 5 from section Running the Performance Design Example (Endpoint) and continue with the steps below.

  1. The Performance Design Example for TL Bypass mode for the R-Tile Avalon Streaming Intel FPGA IP only supports menu option 9. Enter 9 and press Enter to proceed.

  2. Select the R-Tile PCIe Hard IP mode.
    Note: For the Performance Design Example for TL Bypass mode, only the 1x16 R-Tile PCIe Hard IP Mode is supported in the current release of the Quartus® Prime software.

  3. Select the End Point Originated Traffic. For the Performance Design Example for TL Bypass mode with 1x16 R-Tile PCIe Hard IP Mode, you are allowed to run the Max Performance Test or Custom Performance Test.

  4. The option 0: Run Max Performance Test generates Memory Write traffic, Memory Read traffic and simultaneous Memory Write and Memory Read Traffic with the payload size and read request size that allow you to obtain the maximum performance.

  5. The option 1: Run Custom Performance Test allows you to configure the traffic sent during the performance test. By selecting this option, you are able to enter the number of iterations to be carried out, the Payload Size for Memory transactions, the Read Request Size for Memory Read transactions, as well as the type of traffic to execute.